Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    CY7C1380B167AI Search Results

    SF Impression Pixel

    CY7C1380B167AI Price and Stock

    Rochester Electronics LLC CY7C1380B-167AI

    IC SRAM 18MBIT PAR 100TQFP
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C1380B-167AI Bulk 10
    • 1 -
    • 10 $31.56
    • 100 $31.56
    • 1000 $31.56
    • 10000 $31.56
    Buy Now

    Cypress Semiconductor CY7C1380B-167AI

    Cache SRAM, 512KX36, 3.4ns PQFP100 '
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Rochester Electronics CY7C1380B-167AI 937 1
    • 1 $30.35
    • 10 $30.35
    • 100 $28.53
    • 1000 $25.8
    • 10000 $25.8
    Buy Now
    Flip Electronics CY7C1380B-167AI 6,088
    • 1 -
    • 10 -
    • 100 -
    • 1000 -
    • 10000 -
    Get Quote

    CY7C1380B167AI Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    CY7C1380B-133AC

    Abstract: CY7C1380B CY7C1382 CY7C1382B
    Text: 380B CY7C1380B CY7C1382B 512K x 36/1M x 18 Pipelined SRAM Features • • • • • • • • • • • Fast clock speed: 200, 167, 150, 133 MHz Provide high-performance 3-1-1-1 access rate Fast OE access times: 3.0, 3.4, 3.8, and 4.2 ns Optimal for depth expansion


    Original
    CY7C1380B CY7C1382B 36/1M CY7C1380B-133AC CY7C1380B CY7C1382 CY7C1382B PDF

    CY7C1380B

    Abstract: CY7C1382 CY7C1382B CY7C1380B167AI CY7C1380B-167AC
    Text: 380B CY7C1380B CY7C1382B 512K x 36/1M x 18 Pipelined SRAM Features isters controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), burst control inputs (ADSC, ADSP, and ADV), write enables (BWa, BWb,


    Original
    CY7C1380B CY7C1382B 36/1M CY7C1380B CY7C1382 CY7C1382B CY7C1380B167AI CY7C1380B-167AC PDF

    CY7C1380B

    Abstract: CY7C1382 CY7C1382B CY7C1380 TWS - 315
    Text: 380B CY7C1380B CY7C1382B 512K x 36/1M x 18 Pipelined SRAM Features isters controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), burst control inputs (ADSC, ADSP, and ADV), write enables (BWa, BWb,


    Original
    CY7C1380B CY7C1382B 36/1M Int01074 CY7C1380B CY7C1382 CY7C1382B CY7C1380 TWS - 315 PDF