CY7C1517V18
Abstract: CY7C1519V18 CY7C1521V18 CY7C1528V18
Text: CY7C1517V18 CY7C1528V18 CY7C1519V18 CY7C1521V18 72-Mbit DDR-II SRAM 4-Word Burst Architecture Features Functional Description • 72-Mbit density 8M x 8, 8M x 9, 4M x 18, 2M x 36 • 300-MHz clock for high bandwidth • 4-Word burst for reducing address bus frequency
|
Original
|
CY7C1517V18
CY7C1528V18
CY7C1519V18
CY7C1521V18
72-Mbit
300-MHz
CY7C1517V18
CY7C1519V18
CY7C1521V18
CY7C1528V18
|
PDF
|
Untitled
Abstract: No abstract text available
Text: CY7C1517V18 CY7C1528V18 CY7C1519V18 CY7C1521V18 72-Mbit DDR-II SRAM 4-Word Burst Architecture Features Functional Description • 72-Mbit density 8M x 8, 8M x 9, 4M x 18, 2M x 36 • 300-MHz clock for high bandwidth • 4-Word burst for reducing address bus frequency
|
Original
|
CY7C1517V18
CY7C1528V18
CY7C1519V18
CY7C1521V18
72-Mbit
300-MHz
|
PDF
|
CY7C1517V18
Abstract: CY7C1519V18 CY7C1521V18 CY7C1528V18
Text: CY7C1517V18 CY7C1528V18 CY7C1519V18 CY7C1521V18 72-Mbit DDR-II SRAM 4-Word Burst Architecture Features Functional Description • 72-Mbit density 8M x 8, 8M x 9, 4M x 18, 2M x 36 • 300-MHz clock for high bandwidth • 4-Word burst for reducing address bus frequency
|
Original
|
CY7C1517V18
CY7C1528V18
CY7C1519V18
CY7C1521V18
72-Mbit
300-MHz
CY7C1517V18
CY7C1519V18
CY7C1521V18
CY7C1528V18
|
PDF
|
Untitled
Abstract: No abstract text available
Text: CY7C1517V18 CY7C1528V18 CY7C1519V18 CY7C1521V18 PRELIMINARY 72-Mbit DDR-II SRAM 4-Word Burst Architecture Features Functional Description • 72-Mbit density 8M x 8, 8M x 9, 4M x 18, 2M x 36 • 300-MHz clock for high bandwidth • 4-Word burst for reducing address bus frequency
|
Original
|
CY7C1517V18
CY7C1528V18
CY7C1519V18
CY7C1521V18
72-Mbit
300-MHz
|
PDF
|
BV25
Abstract: CY7C129 CY7C130 CY7C131 CY7C132 EV25 ev18
Text: CY7C129*DV18/CY7C130*DV25 CY7C130*BV18/CY7C130*BV25/CY7C132*BV25 CY7C131*BV18 / CY7C132*BV18/CY7C139*BV18 CY7C191*BV18/CY7C141*AV18 / CY7C142*AV18/ CY7C151*V18 /CY7C152*V18 Errata Revision: *D March 04, 2008 RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata This document describes the DOFF issue for QDRII/DDRII, the Output Buffer, the JTAG and the DLL issue for
|
Original
|
CY7C129
DV18/CY7C130
CY7C130
BV18/CY7C130
BV25/CY7C132
CY7C131
CY7C132
BV18/CY7C139
CY7C191
BV18/CY7C141
BV25
EV25
ev18
|
PDF
|
05564
Abstract: BV25 CY7C129 CY7C130 CY7C131 CY7C132 CY7C1422AV18 1428A
Text: CY7C129*DV18/CY7C130*DV25 CY7C130*BV18/CY7C130*BV25/CY7C132*BV25 CY7C131*BV18 / CY7C132*BV18/CY7C139*BV18 CY7C191*BV18/CY7C141*AV18 / CY7C142*AV18/ CY7C151*V18 /CY7C152*V18 Errata Revision: *C May 02, 2007 RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata This document describes the DOFF issue for QDRII/DDRII and the Output Buffer and JTAG issues for
|
Original
|
CY7C129
DV18/CY7C130
CY7C130
BV18/CY7C130
BV25/CY7C132
CY7C131
CY7C132
BV18/CY7C139
CY7C191
BV18/CY7C141
05564
BV25
CY7C1422AV18
1428A
|
PDF
|