82V3288
Abstract: BC208 transistor GR-1244-CORE GR-253-CORE IDT82V3288
Text: WAN PLL IDT82V3288 Version 2 June 22, 2006 6024 Silver Creek Valley Road, San Jose, CA 95138 Telephone: 800 345-7015 • TWX: 910-338-2070 • FAX: (408) 284-2775 Printed in U.S.A. 2006 Integrated Device Technology, Inc. DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry
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IDT82V3288
BC208)
BCG208)
82V3288
82V3288
BC208 transistor
GR-1244-CORE
GR-253-CORE
IDT82V3288
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CSR 8510
Abstract: CSR 8510 a10 CSR 8510 v4 80KSBR200 v8 doorbell wireless doorbell 813 doorbell circuit working ADS1118 2322 156 philips doorbell
Text: Advanced Datasheet 80KSBR200 sRIO SERIAL BUFFER FLOW-CONTROL DEVICE Device Overview ◆ The IDT80KSBR200 is a high speed Serial Buffer SerB that can connect to any Serial RapidIO compliant interface. This device is built to work with any sRIO device and especially with the IDT Pre-Processing
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80KSBR200
IDT80KSBR200
IDT70K200.
72Mbit
CSR 8510
CSR 8510 a10
CSR 8510 v4
80KSBR200
v8 doorbell
wireless doorbell 813
doorbell circuit working
ADS1118
2322 156 philips
doorbell
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DOT96
Abstract: No abstract text available
Text: IDTCV146 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE IDTCV146 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR FEATURES: DESCRIPTION: • One high precision PLL for CPU, with SSC and N programmable • One high precision PLL for SRC/PCI/SATA, SSC and N programmable
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IDTCV146
96MHz/48MHz
IDTCV146
200mV
133MHz
100MHz
48MHz
DOT96
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CK410M
Abstract: CK409 CK410B DB400
Text: IDTCV143 1-TO-4 DIFFERENTIAL CLOCK BUFFER COMMERCIAL TEMPERATURE RANGE 1-TO-4 DIFFERENTIAL CLOCK BUFFER DESCRIPTION: FEATURES: • • • • • • • IDTCV143 The CV143 differential buffer is compliant with Intel DB400 specifications. It is intended to distribute the SRC serial reference clock as a companion chip
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IDTCV143
CV143
DB400
CK409,
CK410/CK410M,
CK410B
CK410M
CK409
CK410B
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70P3337
Abstract: 70P3307
Text: PRELIMINARY DATASHEET IDT70P3307 IDT70P3337 1024K/512K x18 SYNCHRONOUS DUAL QDR-IITM Features ◆ 18Mb Density 1024K x 18 – Also available 9Mb Density (512K x 18) QDR-II x 18 Burst-of-2 Interface – Commercial: 233MHz, 250MHz Separate, Independent Read and Write Data Ports
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IDT70P3307
IDT70P3337
1024K/512K
1024K
233MHz,
250MHz
18/9Mb
IDT70P3307/70P3337
70P3337
70P3307
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Untitled
Abstract: No abstract text available
Text: IDT5T93GL02 2.5V LVDS 1:2 GLITCHLESS CLOCK BUFFER TERABUFFER II INDUSTRIAL TEMPERATURE RANGE 2.5V LVDS 1:2 GLITCHLESS CLOCK BUFFER TERABUFFER II DESCRIPTION: FEATURES: • • • • • • • • • • • IDT5T93GL02 The IDT5T93GL02 2.5V differential clock buffer is a user-selectable differential input to two LVDS outputs . The fanout from a differential input to two LVDS
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IDT5T93GL02
IDT5T93GL02
5T93GL02
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Untitled
Abstract: No abstract text available
Text: IDT5T93GL101 2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABUFFER II INDUSTRIAL TEMPERATURE RANGE 2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABUFFER II FEATURES: • • • • • • • • • • • IDT5T93GL101 DESCRIPTION: Guaranteed Low Skew < 75ps max
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IDT5T93GL101
100ps
450MHz
IDT5T93GL101
5T93GL101
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corelis JTAG CONNECTOR
Abstract: PCI-100 asset boundary scan "programmable clock" i2c JTAG CONNECTOR 5T9820NL corelis jtag corelis JTAG CONNECTOR parallel i2c programmable output regulator "Programmable Clock" 6 pin JTAG CONNECTOR
Text: EVALUATION BOARD FOR IDT5T98xx EVALUATION BOARD FOR IDT5T98xx TABLE OF CONTENTS INTRODUCTION Introduction . 1 Board Overview Block Diagram . 1
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IDT5T98xx
10-pin
14-pin
corelis JTAG CONNECTOR
PCI-100 asset boundary scan
"programmable clock" i2c
JTAG CONNECTOR
5T9820NL
corelis jtag
corelis JTAG CONNECTOR parallel
i2c programmable output regulator
"Programmable Clock"
6 pin JTAG CONNECTOR
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diode in40
Abstract: Diode Mark ON B14 Q127 xn13
Text: 1.8V MULTI-QUEUE FLOW-CONTROL DEVICES 128 QUEUES 40 BIT WIDE CONFIGURATION IDT72P51767 IDT72P51777 5,242,880 bits 10,485,760 bits FEATURES • • • • • • • • • • • • Choose from among the following memory density options: IDT72P51767 Total Available Memory = 5,242,880 bits
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IDT72P51767
IDT72P51777
IDT72P51767:
IDT72P51777:
acce72P51767
72P51777
drw79
diode in40
Diode Mark ON B14
Q127
xn13
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CK410
Abstract: CK409 CK410B DB1200G DSC67
Text: IDTCV128 1-TO-12 DIFFERENTIAL CLOCK BUFFER COMMERCIAL TEMPERATURE RANGE 1-TO-12 DIFFERENTIAL CLOCK BUFFER IDTCV128 DESCRIPTION: FEATURES: The CV128 differential buffer complies with Intel DB1200G rev. 0.5, and is designed to work in conjunction with the main clock of CK409, CK410/CK410M
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IDTCV128
1-TO-12
CV128
DB1200G
CK409,
CK410/CK410M
CK410B
CK410
CK409
DSC67
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Untitled
Abstract: No abstract text available
Text: 1.8V MULTI-QUEUE FLOW-CONTROL DEVICES 128 QUEUES 36 BIT WIDE CONFIGURATION 1,179,648 bits 2,359,296 bits 4,718,592 bits • FEATURES • • • • • • • • • Choose from among the following memory density options: IDT72P51749 Total Available Memory = 1,179,648 bits
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IDT72P51749
IDT72P51759
IDT72P51769
IDT72P51749
IDT72P51759
IDT72P51749:
IDT72P51759:
IDT72P51769:
BB256-1)
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Untitled
Abstract: No abstract text available
Text: IDT5T93GL061 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II INDUSTRIAL TEMPERATURE RANGE 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II DESCRIPTION: FEATURES: • • • • • • • • • • • IDT5T93GL061 The IDT5T93GL061 2.5V differential clock buffer is a user-selectable
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IDT5T93GL061
100ps
450MHz
IDT5T93GL061
5T93GL061
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Untitled
Abstract: No abstract text available
Text: DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT IDT82V2052E FEATURES: • • • • • Dual channel E1 short haul line interfaces Supports HPS Hitless Protection Switching for 1+1 protection without external relays Single 3.3 V power supply with 5 V tolerance on digital interfaces
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IDT82V2052E
TBR12/13
Figure-32
82V2052E
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Untitled
Abstract: No abstract text available
Text: 1.8V MULTI-QUEUE FLOW-CONTROL DEVICES 8 QUEUES 36 BIT WIDE CONFIGURATION 589,824 bits 1,179,648 bits 2,359,296 bits 4,718,592 bits • FEATURES • • • • • • • • • Choose from among the following memory density options: IDT72P51339 Total Available Memory = 589,824 bits
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IDT72P51339
IDT72P51349
IDT72P51359
IDT72P51369
IDT72P51339:
IDT72P51349:
IDT72P51359:
IDT72P51369:
72P51339
72P51349
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Untitled
Abstract: No abstract text available
Text: SINGLE CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT IDT82V2041E FEATURES Single channel T1/E1/J1 short haul line interfaces Supports HPS Hitless Protection Switching for 1+1 protection without external relays Programmable T1/E1/J1 switchability allowing one bill of material for any line condition
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IDT82V2041E
TBR12/13
IDT82P2816
PPG44)
82V2041E
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Table-49
Abstract: IDT82V2041E TQFP44
Text: SINGLE CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT IDT82V2041E FEATURES • • • • • • Single channel T1/E1/J1 short haul line interfaces Supports HPS Hitless Protection Switching for 1+1 protection without external relays Programmable T1/E1/J1 switchability allowing one bill of material for any line condition
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IDT82V2041E
TBR12/13
IDT82P2816
PPG44)
82V2041E
Table-49
IDT82V2041E
TQFP44
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IC-7031
Abstract: 82V2082 IDT82V2052E LP21 TQFP80
Text: DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT IDT82V2052E FEATURES: • • • • • Dual channel E1 short haul line interfaces Supports HPS Hitless Protection Switching for 1+1 protection without external relays Single 3.3 V power supply with 5 V tolerance on digital interfaces
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IDT82V2052E
TBR12/13
CHARACTERISTICS69
82V2052E
PNG80)
IC-7031
82V2082
IDT82V2052E
LP21
TQFP80
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GR-1244-CORE
Abstract: GR-253-CORE IDT82V3280 GR-1377-CORE 19.440 MHz TCXO
Text: WAN PLL IDT82V3280 Version 2 June 19, 2006 6024 Silver Creek Valley Road, San Jose, CA 95138 Telephone: 800 345-7015 • TWX: 910-338-2070 • FAX: (408) 284-2775 Printed in U.S.A. 2006 Integrated Device Technology, Inc. DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry
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IDT82V3280
PN100)
PNG100)
DQ100)
DQG100)
82V3280
GR-1244-CORE
GR-253-CORE
IDT82V3280
GR-1377-CORE
19.440 MHz TCXO
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circuit diagram for automatic voltage regulator G
Abstract: GR-1244-CORE GR-253-CORE IDT82V3255
Text: WAN PLL IDT82V3255 Version 2 June 19, 2006 6024 Silver Creek Valley Road, San Jose, CA 95138 Telephone: 800 345-7015 • TWX: 910-338-2070 • FAX: (408) 284-2775 Printed in U.S.A. 2006 Integrated Device Technology, Inc. DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry
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IDT82V3255
PPG64)
DKG64)
82V3255
circuit diagram for automatic voltage regulator G
GR-1244-CORE
GR-253-CORE
IDT82V3255
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XN07
Abstract: Q127 wd2m
Text: 1.8V MULTI-QUEUE FLOW-CONTROL DEVICES 128 QUEUES 40 BIT WIDE CONFIGURATION IDT72P51767 IDT72P51777 5,242,880 bits 10,485,760 bits FEATURES • • • • • • • • • • • • Choose from among the following memory density options: IDT72P51767 ⎯ Total Available Memory = 5,242,880 bits
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IDT72P51767
IDT72P51777
IDT72P51767:
IDT72P51777:
drw79
XN07
Q127
wd2m
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Untitled
Abstract: No abstract text available
Text: IDT5T93GL101 2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABUFFER II INDUSTRIAL TEMPERATURE RANGE 2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABUFFER II FEATURES: • • • • • • • • • • • IDT5T93GL101 DESCRIPTION: Guaranteed Low Skew < 75ps max
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IDT5T93GL101
100ps
450MHz
IDT5T93GL101
5T93GL101
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Untitled
Abstract: No abstract text available
Text: IDT5T93GL061 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II INDUSTRIAL TEMPERATURE RANGE 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II DESCRIPTION: FEATURES: • • • • • • • • • • • IDT5T93GL061 The IDT5T93GL061 2.5V differential clock buffer is a user-selectable
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IDT5T93GL061
IDT5T93GL061
5T93GL061
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Untitled
Abstract: No abstract text available
Text: 1.8V MULTI-QUEUE FLOW-CONTROL DEVICES 8 QUEUES 36 BIT WIDE CONFIGURATION 589,824 bits 1,179,648 bits 2,359,296 bits 4,718,592 bits • FEATURES • • • • • • • • • Choose from among the following memory density options: IDT72P51339 Total Available Memory = 589,824 bits
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IDT72P51339
IDT72P51349
IDT72P51359
IDT72P51369
IDT72P51339:
IDT72P51349:
IDT72P51359:
IDT72P51369:
72P51339
72P51349
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LP21
Abstract: TQFP80 PULS12
Text: DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT IDT82V2042E FEATURES: • • • • • • Dual channel T1/E1/J1 short haul line interfaces Supports HPS Hitless Protection Switching for 1+1 protection without external relays Programmable T1/E1/J1 switchability allowing one bill of material for any line condition
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IDT82V2042E
TBR12/13
82V2042E
LP21
TQFP80
PULS12
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