27c040-10
Abstract: 27C040-12 1S84 8332 memory 27C040-15 SMJ27C040
Text: SMJ27C040 4194304-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY SGMS046A- NOVEMBER 1992 - REVISED JUNE 1995 J PACKAGE Organization . . . 512K x 8 Single 5-V Power Supply Industry Standard 32-Pin Dual-in-line Package All inputs/Outputs Fully TTL Compatible
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SMJ27C040
4194304-BIT
SGMS046A-
32-Pin
27C040-10
27C040-12
27C040-15
400-mV
SMJ27C040
1S84
8332 memory
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2U97
Abstract: No abstract text available
Text: TMS626402 2097152-WORD BY 4-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY SMOS642A- FEBRUARY 1994 - REVISED JUNE 1995 DGEPACKAGE TOP VIEW • Organization . . . 2M x 4 x 2 Banks • 3.3-V Power Supply (±10% Tolerance) • TWo Banks for On-Chip Interleaving
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TMS626402
2097152-WORD
SMOS642A-
100-MHz
2U97
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27C512JL
Abstract: 1985-REVISED TMS27C512 27pc512 Texas Instruments TTL 1985 TMS27PC512 -12nt 512K x 8 High Performance CMOS EPROM TMS27PC512 lt 637 CODE ZA10
Text: TMS27C512 524 288-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC512 524 288-BIT PROGRAMMABLE READ-ONLY MEMORY • T II5 S M LS 512E-N O VE M B ER 19 8 5 -R E V IS E D DECEM BER 1992 This Data Sheet is Applicable to All TMS27C512S and TMS27PC512s Symbolized with Code “B" as Described
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TMS27C512
288-BIT
TMS27PC512
SMLS512E-NOVEMBER
1985-REVISED
TMS27C512S
TMS27PC512s
27C/PC512-10
27C/PC512-12
27C512JL
27pc512
Texas Instruments TTL 1985
TMS27PC512 -12nt
512K x 8 High Performance CMOS EPROM
lt 637
CODE ZA10
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PDF
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4C1024
Abstract: SGM 430 zig bee T 2109 ti 4c1024 SMJ44C256 SMJ4C1024
Text: • L2 E D ■ TEXAS I N S T R 6Tbl7ES OOâl ObO 2 T 0 ■ T I I S SMJ4C1024 1 048 576-BIT DYNAMIC RANDOM-ACCESS MEMORY ASIC/MEMORY SGMS023B-DEC EMBER 1988-REVISED MARCH 1992 Processed to MIL-STD-883, Class B Operating Temperature Range . . . - 55°C to 125°C
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SMJ4C1024
576-BIT
SGMS023B-DECEMBER1988-REVISED
MIL-STD-883,
4C1024-80
4C1024-10
4C1024-12
4C1024-15
1988-REVISED
4C1024
SGM 430
zig bee
T 2109
ti 4c1024
SMJ44C256
SMJ4C1024
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PDF
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1S14
Abstract: No abstract text available
Text: S M J S 8 1 6 B - N O V E M B E R 19 9 0 - R E V I S E D J A N U A R Y 1 9 9 3 FM PACKAGEt TOP VIEW Member of Texas Instruments SCOPE Family of Testability Products L_JI 2 Organization . . . 2048 x 8-Bit Flash Memory il il I 1 18 17 O 3 TMS 4 TCK 5 NC
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TMS29F816
384-BIT
SMJS81
1990-REVISED
29F816-06
1024-Byte
32-Byte
18-Pin
1S14
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Untitled
Abstract: No abstract text available
Text: • 0^1725 007715=1 T ■ T-46-13-25 TMS27C49 65,536-BIT UV. ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC49 65,536-BIT PROGRAMMABLE READ-ONLY MEMORY A SI C/M EMO RY 5SE I> EPROMs/PROMs/EEPROMs TE XAS IN ST R . Te x a s ^ In s t r u m e n t s PO ST OFFICÊ B O X 1443 • HOUSTON, T É X A S 77001
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T-46-13-25
TMS27C49
536-BIT
TMS27PC49
00771bG
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A31-1
Abstract: No abstract text available
Text: TEXAS INSTR ASIC/MEMORY 77C D • 0^1725 G0M0Ö41 =1 TM4256FL8, TM4256GU8, TM4257FL8, TM4257GU8 262,144 BY 8 BIT DYNAMIC RAM MODULES ADVANCE INFORMATION ISEO NOVEMBER 1985 OCTOBER 1985 - REVISEI T M 4 2 5 .F L 8 . . . L SINGLE-IN-LINE PACKAGE 2 6 2 ,1 4 4 X 8 Organization
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TM4256FL8,
TM4256GU8,
TM4257FL8,
TM4257GU8
30-Pin
fl1bl725
A31-1
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TM124MBK36B
Abstract: TM124MBK36R TM248NBK36B TM248NBK36R
Text: S M M S 1 3 7 D -J A N U A R Y 1 9 9 1 - R E V IS E D J A N U A R Y 1 9 9 3 * * * ACCESS ACCESS READ TIME TIME OR •RAC *AA tC AC WRITE MAX (MAX) (MAX) (MIN) ‘124MBK36B-60 60 ns 30 ns 15 ns 110 ns •124MBK36B-70 ’124MBK36B-80 70 ns 80 ns 35 ns 40 ns
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TM124MBK36B,
TM124MBK36R
36-BIT
TM248NBK36B,
TM248NBK36R
SMMS137D-JANUARY
1991-REVISED
124MBK36B-60
124MBK36B-70
TM124MBK36B
TM248NBK36B
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Untitled
Abstract: No abstract text available
Text: TMS370Cx4x 8-BIT MICROCONTROLLERS SP S N O I6- N O V E M B E R 1992 J, N AND N2 PACKAGESt TOP VIEW CMOS/EEPROM/EPROM Technologies on a Single Device - Mask ROM Devices for High Volume Production - One-Time Programmable (OTP) Devices for Low Volume Production
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TMS370Cx4x
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TMS28F040
Abstract: No abstract text available
Text: LEE TEXAS D • INSTR 6Tbl7SS D 0f l0 7f lT 7TS ■ T I I 5 _ _ TMS28F040 4 194 304-BIT FLASH ELECTRICALLY ERASABLE ASIC/flEMORY PROGRAMMABLE READ-ONLY MEMORY S M JS 0 4 0 -D E C E M B E R 1992 Organization . . . 512K x 8 Separately Erasable 32K Byte Blocks
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TMS28F040
304-BIT
A0-A18
32-pin
40-pin
TMS28F040
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PDF
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h1a11
Abstract: mip 2h2 320C5X BDX 647 C TMDS3200051 MIP 411 MP 7721 TMS320C5x architecture diagram TCO 976 TMS320C25
Text: TMS320C5X, TMS320LC5X DIGITAL SIGNAL PROCESSORS SP R S 030A - APRIL 1995 - R EVISED APRIL 1996 • Powerful 16-Bit TMS320C5x CPU • 20-, 25-, 35-, and 50-ns Single-Cycle Instruction Execution Time for 5-V Operation • Multiple Phase-Locked Loop PLL Clocking Options (x1, x2, x3, x4, x5, x9
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16-Bit
TMS320C5x
50-ns
JEDECMO-136
TMS320C5X,
h1a11
mip 2h2
320C5X
BDX 647 C
TMDS3200051
MIP 411
MP 7721
TMS320C5x architecture diagram
TCO 976
TMS320C25
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