Untitled
Abstract: No abstract text available
Text: Signetics 54F113 Flip-Flop Dual J-K Negative Edge-Triggered Flip-Flop Without Reset Product Specification Military Logic Products DESCRIPTION The 54F113 is a dual J-K negative edge-triggered flip-flop featuring indi vidual J, K, Set and Clock inputs. The
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54F113
54F113
500ns
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TC40H076AP
Abstract: AH120 A140S TC40H076P TC40H76AP
Text: TOSHIBA INTEGRATED CIRCUIT TECHNICAL DATA Æ TC40H076P/F TC40H076AP/AF C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC40H076 TC40H076A DUAL J-K FLIP-FLOP PULSE TRIGGER TYPE DUAL J-K FLIP-FLOP (EDGE TRIGGER TYPE) The TC40H076 is a dual J-K flip-flop with
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TC40H076P/F
TC40H076AP/AF
TC40H076
TC40H076A
TC40H076A,
3d13a-p)
TC40H076AP
AH120
A140S
TC40H076P
TC40H76AP
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Untitled
Abstract: No abstract text available
Text: m jé National Semiconductor DM74AS109 Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and Clear General Description Features The ’AS109 is a dual edge-triggered flip-flop. Each flip-flop has individual J, K, clock, clear and preset inputs, and also
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DM74AS109
AS109
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74107 pin diagram
Abstract: CI 74107 74ls107 pin configuration 74LS107 TTL 74107 2RD22 74107 LS107 1N3064 1N916
Text: Signetics 74107, LS107 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The ’107 is a dual flip-flop with individual J, K, Clock and direct Reset inputs. The 74107 is a positive pulse-triggered flip flop. JK information is loaded into the
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LS107
74LS107
1N916,
1N3064,
500ns
74107 pin diagram
CI 74107
pin configuration 74LS107
TTL 74107
2RD22
74107
LS107
1N3064
1N916
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Untitled
Abstract: No abstract text available
Text: IDT74LVC112A 3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS DUAL IDT74LVC112A NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET, 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: This dual negative-edge-triggered J-K flip-flop is built using advanced
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IDT74LVC112A
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C1995
Abstract: DM74ALS DM74ALS109A DM74ALS109AM DM74ALS109AN LS109 M16A N16A
Text: DM74ALS109A Dual J-K PositiveEdge-Triggered Flip-Flop with Preset and Clear General Description Features The DM54ALS109A is a dual edge-triggered flip-flop Each flip-flop has individual J K clock clear and preset inputs and also complementary Q and Q outputs
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DM74ALS109A
DM54ALS109A
C1995
DM74ALS
DM74ALS109AM
DM74ALS109AN
LS109
M16A
N16A
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14027B
Abstract: HD14027B
Text: HD14027B Dual J - K Flip Flop The HD14027B dual J-K flip-flop has independent J, K, Clock C , Set(S) and Reset(R) inputs for each flip-flop. These devices may be used in control, register, or toggle functions. • PIN ARRANGEMENT ■ FEATURES • • •
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HD14027B
HD14027B
CD4027B
MC14027B
K20ns
14027B
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8 way flip-flop ic
Abstract: IDT74LVC112A LVC112A
Text: IDT74LVC112A 3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS DUAL IDT74LVC112A NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET, 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: This dual negative-edge-triggered J-K flip-flop is built using advanced
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IDT74LVC112A
8 way flip-flop ic
IDT74LVC112A
LVC112A
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Untitled
Abstract: No abstract text available
Text: 54LS109 Signetics Flip-Flop Dual J-K Positive Edge-Triggered Flip-Flop Product Specification Military Logic Products DESCRIPTION The 54LS109 is a dual positive edge-trig gered JK-type flip-flop featuring individual J, K, Clock, Set and Reset inputs; also
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54LS109
54LS109
54LSXXX
500ns
S15ns
1N916
1N3064,
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Untitled
Abstract: No abstract text available
Text: MOTOROLA DUAL J-K FLIP-FLOP MC14027B The MC14Q27B dual J-K flip-flop has independent J, K, Clock {Q, Set S and Reset |R) inputs for each flip-flop. These devices may be used in control, register, or toggle functions. CMOS SSI • • Diode Protection on A ll Inputs
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MC14Q27B
MC14027B
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54S112
Abstract: totempole d2302
Text: Signetics 54S 112 Flip-Flop Dual J-K Edge-Triggered Flip-Flop Product Specification Military Logic Products DESCRIPTION The 54S112 is a dual J-K negative edge-triggered flip-flop featuring individu al J, K, Clock, Set and Reset inputs. The Set 5d and Reset (RD) inputs, when Low,
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54S112
54S112
54SXXX
500ns
1N916
1N3064,
totempole
d2302
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ECL 10135
Abstract: 10135 jk flipflop 425 10135F 10135N 10135dc ecl 10K signetics
Text: Signetics 10135 Flip-Flop Dual J-K Master-Slave Flip-Flop P roduct Specification ECL Products DESCRIPTION The 10135 is a Dual Master-Slave DC coupled J-K Flip-Flop. It contains a com mon clock and separate J-K inputs which do not affect the output when the
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10135N
10135F
800mVp-p
500ns
ECL 10135
10135
jk flipflop 425
10135F
10135N
10135dc
ecl 10K signetics
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DM74ALS
Abstract: DM74ALS109A DM74ALS109AM DM74ALS109AN LS109 M16A N16A DM74ALS109
Text: DM74ALS109A Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and Clear General Description Features The DM54ALS109A is a dual edge-triggered flip-flop. Each flip-flop has individual J, K, clock, clear and preset inputs, and also complementary Q and Q outputs.
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DM74ALS109A
DM54ALS109A
DM74ALS
DM74ALS109A
DM74ALS109AM
DM74ALS109AN
LS109
M16A
N16A
DM74ALS109
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LCX112
Abstract: 74LCX112 74LCX112M 74LCX112MTC 74LCX112SJ M16A M16D MTC16 DSA0031497
Text: Revised August 1998 74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs General Description Features The LCX112 is a dual J-K flip-flop. Each flip-flop has independent J, K, PRESET, CLEAR, and CLOCK inputs with Q, Q outputs. These devices are edge sensitive and change
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74LCX112
LCX112
74LCX112
74LCX112M
74LCX112MTC
74LCX112SJ
M16A
M16D
MTC16
DSA0031497
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Untitled
Abstract: No abstract text available
Text: December 1989 Semiconductor DM74ALS109A Dual J-K PositiveEdge-Triggered Flip-Flop with Preset and Clear General Description Features The DM54ALS109A is a dual edge-triggered flip-flop. Each flip-flop has individual J, K, clock, clear and preset inputs, and also complementary Q and Q outputs.
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DM74ALS109A
DM54ALS109A
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LCX112
Abstract: MTC16 74LCX112 74LCX112M 74LCX112MTC 74LCX112SJ M16A M16D
Text: Revised February 2001 74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs General Description Features The LCX112 is a dual J-K flip-flop. Each flip-flop has independent J, K, PRESET, CLEAR, and CLOCK inputs with Q, Q outputs. These devices are edge sensitive and change
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74LCX112
LCX112
74LCX112
MTC16
74LCX112M
74LCX112MTC
74LCX112SJ
M16A
M16D
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74LCX112
Abstract: 74LCX112M 74LCX112MTC 74LCX112SJ LCX112 M16A M16D MTC16
Text: Revised March 1999 74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs General Description Features The LCX112 is a dual J-K flip-flop. Each flip-flop has independent J, K, PRESET, CLEAR, and CLOCK inputs with Q, Q outputs. These devices are edge sensitive and change
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74LCX112
LCX112
74LCX112
74LCX112M
74LCX112MTC
74LCX112SJ
M16A
M16D
MTC16
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Untitled
Abstract: No abstract text available
Text: 109 A National Semiconductor DM74ALS109A Dual J-K PositiveEdge-Triggered Flip-Flop with Preset and Clear General Description Features The DM54ALS109A is a dual edge-triggered flip-flop. Each flip-flop has individual J, K, clock, clear and preset inputs, and also complementary Q and Q outputs.
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DM74ALS109A
DM54ALS109A
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Untitled
Abstract: No abstract text available
Text: MC14025B See Page 6-5 MOTOROLA MCM025U8 See Page 6-14 MC14027B DUAL J-K FLIP-FLOP The M C14027B dual J-K flip-flop has independent J , K , Clock C , Set (S) and Reset (R ) inputs for each flip-flop. These devices may be used in control, register, or toggle functions.
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MC14025B
MCM025U8
MC14027B
C14027B
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74107 pin diagram
Abstract: 74107 74LS107 74107 flip flop H/CI 74107 pin configuration 74LS107 1N3064 1N916 74LS LS107
Text: 74107, LS107 Signetics Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION Th e '1 0 7 is a dual flip-flop with individual J, K, Clock and direct R eset inputs. The 7 4 1 0 7 Is a positive pulse-triggered flip flop. JK information is loaded into the
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74LS107
1N916,
1N3064,
500ns
74107 pin diagram
74107
74107 flip flop
H/CI 74107
pin configuration 74LS107
1N3064
1N916
74LS
LS107
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Untitled
Abstract: No abstract text available
Text: Revised August 1998 SE M IC O N D U C TO R TM 74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs General Description Features The LCX112 is a dual J-K flip-flop. Each flip-flop has inde£endent J, K, PRESET, CLEAR, and CLOCK inputs with Q,
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74LCX112
LCX112
74LCX112
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54F109
Abstract: No abstract text available
Text: Philips Semiconductors Military FAST Products Product specification Flip-flop 54F109 DESCRIPTION The JK design allows operation as a D flip-flop by tying the J and K inputs together. The 54F109 is a dual positive edge-triggered JK*type flip-flop featuring individual J, K, Clock, Set and Reset inputs, and
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54F109
54F109
500ns
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54LS112
Abstract: No abstract text available
Text: M MOTOROLA M ilitary 54LS112A Dual J -K Flip-Flop W ith C lear and P reset MPO lllflll ELECTRICALLY TESTED PER: MIL-M-38510/30103 The 54LS112A dual flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes
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MIL-M-38510/30103
54LS112A
54LS112A
JM38510/30103BXA
54LS112A/BXAJC
54LS112
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MHTL
Abstract: "J-K Flip flop" LANSDALE SEMICONDUCTOR ML688T MC688T
Text: ML688T Dual J-K Flip-Flop Legacy Device: Motorola MC688T The negative–edge–clocked dual J-K flip-flop operates on the master–slave principle. His device provides both SET and RESET inputs on both flip-flops in the package. Each flip-flop may be set or reset by applying a low level to that particular
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ML688T
MC688T
MHTL
"J-K Flip flop"
LANSDALE SEMICONDUCTOR
ML688T
MC688T
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