Untitled
Abstract: No abstract text available
Text: Preliminary GS81302T08/09/18/36E-375/350/333/300/250 144Mb SigmaDDRTM-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 375 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus
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Original
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PDF
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GS81302T08/09/18/36E-375/350/333/300/250
165-Bump
165-bump,
GS81302Txx
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Untitled
Abstract: No abstract text available
Text: GS81302T08/09/18/36E-375/350/333/300/250 144Mb SigmaDDRTM-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 375 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package
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Original
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PDF
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GS81302T08/09/18/36E-375/350/333/300/250
165-Bump
165-bump,
144Mb
GS81302Txx
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Untitled
Abstract: No abstract text available
Text: Preliminary GS81302T07/10/19/37E-400/375/333/300 144Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 400 MHz–300 MHz 1.8 V VDD 1.8 V or 1.5 V I/O Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface
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Original
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PDF
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GS81302T07/10/19/37E-400/375/333/300
165-Bump
165-bump,
GS81302Txx
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Untitled
Abstract: No abstract text available
Text: GS81302T07/10/19/37E-450/400/350/333/300 144Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package
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Original
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PDF
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GS81302T07/10/19/37E-450/400/350/333/300
144Mb
165-Bump
GS81302T1937
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Untitled
Abstract: No abstract text available
Text: GS81302T08/09/18/36E-375/350/333/300/250 144Mb SigmaDDRTM-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface
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Original
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PDF
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GS81302T08/09/18/36E-375/350/333/300/250
165-Bump
165-bump,
144Mb
GS81302Txx
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CQ 765
Abstract: No abstract text available
Text: GS81302T07/10/19/37E-450/400/350/333/300 144Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package
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Original
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PDF
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GS81302T07/10/19/37E-450/400/350/333/300
144Mb
165-Bump
GS81302T1937
CQ 765
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GS81302T36GE-333
Abstract: No abstract text available
Text: Preliminary GS81302T08/09/18/36E-333/300/250/200/167 144Mb SigmaDDRTM-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus
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Original
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PDF
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GS81302T08/09/18/36E-333/300/250/200/167
144Mb
165-Bump
72M6E-333/300/250/200/167
GS81302Txx
GS81302T36GE-333
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Untitled
Abstract: No abstract text available
Text: Preliminary GS81302T08/09/18/36E-333/300/250/200/167 144Mb SigmaDDRTM-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus
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Original
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PDF
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GS81302T08/09/18/36E-333/300/250/200/167
165-Bump
165-bump,
GS81302Txx
|
Untitled
Abstract: No abstract text available
Text: Preliminary GS81302T07/10/19/37E-450/400/350/333/300 144Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 450 MHz–300 MHz 1.8 V VDD 1.8 V or 1.5 V I/O Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface
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Original
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PDF
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GS81302T07/10/19/37E-450/400/350/333/300
165-Bump
165-bump,
GS81302T1937
|
Untitled
Abstract: No abstract text available
Text: Preliminary GS81302T08/09/18/36E-333/300/250/200/167 144Mb SigmaCIO DDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus
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Original
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PDF
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GS81302T08/09/18/36E-333/300/250/200/167
144Mb
165-Bump
GS8130x36E-300T.
GS81302Txx
|
GS81302T18GE-333
Abstract: No abstract text available
Text: GS81302T08/09/18/36E-375/350/333/300/250 144Mb SigmaDDRTM-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface
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Original
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PDF
|
GS81302T08/09/18/36E-375/350/333/300/250
144Mb
165-Bump
165-bump,
GS81302Txx
GS81302T18GE-333
|
Untitled
Abstract: No abstract text available
Text: GS81302T08/09/18/36E-375/350/333/300/250 144Mb SigmaDDRTM-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface
|
Original
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PDF
|
GS81302T08/09/18/36E-375/350/333/300/250
144Mb
165-Bump
165-bump,
GS81302Txx
|
Untitled
Abstract: No abstract text available
Text: Preliminary GS81302T08/09/18/36E-333/300/250/200/167 144Mb SigmaCIO DDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus
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Original
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PDF
|
GS81302T08/09/18/36E-333/300/250/200/167
165-Bump
165-bump,
GS8130x36E-300T.
GS81302Txx
|
Untitled
Abstract: No abstract text available
Text: GS81302T07/10/19/37E-450/400/350/333/300 144Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package
|
Original
|
PDF
|
GS81302T07/10/19/37E-450/400/350/333/300
144Mb
165-Bump
GS81302T1937
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