CY7C1360A1-150AC
Abstract: CY7C1362A1 GVT71512DA18
Text: CY7C1360A1/GVT71256DA36 CY7C1362A1/GVT71512DA18 PRELIMINARY 256K x 36/512K x 18 Pipelined SRAM eral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining
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CY7C1360A1/GVT71256DA36
CY7C1362A1/GVT71512DA18
36/512K
CY7C1360A1-150AC
CY7C1362A1
GVT71512DA18
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