HEP51
Abstract: KEP51 MC100EP51 MC10EP51 LVEL51
Text: MC10EP51, MC100EP51 3.3V / 5VĄECL D Flip-Flop with Reset and Differential Clock The MC10/100EP51 is a differential clock D flip–flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices. The reset input is an asynchronous, level triggered signal. Data
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Original
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MC10EP51,
MC100EP51
MC10/100EP51
LVEL51
r14525
MC10EP51/D
HEP51
KEP51
MC100EP51
MC10EP51
LVEL51
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PDF
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HEP51
Abstract: KEP51 MC100EP51 MC10EP51
Text: MC10EP51, MC100EP51 3.3V / 5V ECL D Flip−Flop with Reset and Differential Clock Description The MC10/100EP51 is a differential clock D flip−flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices. The reset input is an asynchronous, level triggered signal. Data
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Original
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MC10EP51,
MC100EP51
MC10/100EP51
LVEL51
MC10EP51/D
HEP51
KEP51
MC100EP51
MC10EP51
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PDF
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KLT20
Abstract: k1648 klt22 KEL32 MC100 HEP64 KLT21 LP17 KEP32 HEP139
Text: AND8002/D ECLinPS, ECLinPS Lite, ECLinPS Plus, ECLinPS MAX, and GigaComm Marking and Ordering Information Guide http://onsemi.com APPLICATION NOTE Prepared by: Paul Shockman ON Semiconductor HFPD Applications Engineer Introduction This application note describes the device markings and
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Original
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AND8002/D
KLT20
k1648
klt22
KEL32
MC100
HEP64
KLT21
LP17
KEP32
HEP139
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PDF
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motorola HEP cross reference
Abstract: EPT 4045 KPT23 motorola HEP 320 cross reference vef 202 manual KEP52 MC10EP016 HEP 801 hep51 HEP64
Text: BR1513/D Rev. 2, Apr-2001 ECLinPS Plus Device Data ECLinPS Plus Device Data Advanced ECL in Picoseconds BR1513/D Rev. 2, Apr–2001 SCILLC, 2001 Previous Edition 2000 “All Rights Reserved” ECLinPS, ECLinPS Lite, and ECLinPS Plus are trademarks of Semiconductor Components Industries, LLC.
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Original
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BR1513/D
Apr-2001
r14525
DLD601
motorola HEP cross reference
EPT 4045
KPT23
motorola HEP 320 cross reference
vef 202 manual
KEP52
MC10EP016
HEP 801
hep51
HEP64
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PDF
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kvt22
Abstract: KVL11 KPT23 ON Semiconductor marking k1648 KLT20 HEL16 KEL32 KEL01 xaa9646
Text: AND8002/D ECLinPS, ECLinPS Lite and ECLinPS Plus Device Type and Date Code Marking Guide Gary Richards, ECL Logic Product Engineering http://onsemi.com APPLICATION NOTE need ON Semiconductor’s marking spec 12MON00232D and S.O.P. 7–19 ID of Products to Location of
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Original
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AND8002/D
12MON00232D
r14525
kvt22
KVL11
KPT23
ON Semiconductor marking
k1648
KLT20
HEL16
KEL32
KEL01
xaa9646
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PDF
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KEP51
Abstract: HK-5-S mc100ep51dg HEP51 MC100EP51 MC10EP51 MC100EP51DTG
Text: MC10EP51, MC100EP51 3.3V / 5V ECL D Flip−Flop with Reset and Differential Clock Description The MC10/100EP51 is a differential clock D flip−flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices. The reset input is an asynchronous, level triggered signal. Data
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Original
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MC10EP51,
MC100EP51
MC10/100EP51
LVEL51
MC10EP51/D
KEP51
HK-5-S
mc100ep51dg
HEP51
MC100EP51
MC10EP51
MC100EP51DTG
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PDF
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HEP51
Abstract: KEP51 MC100EP51 MC10EP51
Text: MC10EP51, MC100EP51 3.3V / 5V ECL D Flip-Flop with Reset and Differential Clock Description The MC10/100EP51 is a differential clock D flip−flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices. The reset input is an asynchronous, level triggered signal. Data
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Original
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MC10EP51,
MC100EP51
MC10/100EP51
LVEL51
MC10EP51/D
HEP51
KEP51
MC100EP51
MC10EP51
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PDF
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hep51
Abstract: TIP 3055 JAPAN transistor tip 3055
Text: MC10EP51, MC100EP51 3.3V / 5V ECL D Flip-Flop with Reset and Differential Clock Description The MC10/100EP51 is a differential clock D flip−flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices. The reset input is an asynchronous, level triggered signal. Data
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Original
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MC10EP51,
MC100EP51
MC10/100EP51
LVEL51
MC10EP51/D
hep51
TIP 3055 JAPAN
transistor tip 3055
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PDF
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HEP51
Abstract: KEP51 MC100EP51 MC10EP51 MC100EP51MNR4G
Text: MC10EP51, MC100EP51 3.3V / 5V ECL D Flip−Flop with Reset and Differential Clock Description The MC10/100EP51 is a differential clock D flip−flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices. The reset input is an asynchronous, level triggered signal. Data
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Original
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MC10EP51,
MC100EP51
MC10/100EP51
LVEL51
MC10EP51/D
HEP51
KEP51
MC100EP51
MC10EP51
MC100EP51MNR4G
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PDF
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HEP51
Abstract: KEP51 MC100 MC100EP51 MC10EP51 HEP-51
Text: MC10EP51, MC100EP51 Product Preview D Flip Flop with Set and Reset The MC10/100EP51 is a differential clock D flip-flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices. The reset input is an asynchronous, level triggered signal. Data
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Original
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MC10EP51,
MC100EP51
MC10/100EP51
LVEL51
r14525
MC10EP51/D
HEP51
KEP51
MC100
MC100EP51
MC10EP51
HEP-51
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PDF
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tip 3055
Abstract: No abstract text available
Text: MC10EP51, MC100EP51 3.3V / 5V ECL D Flip-Flop with Reset and Differential Clock Description The MC10/100EP51 is a differential clock D flip−flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices. The reset input is an asynchronous, level triggered signal. Data
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Original
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MC10EP51,
MC100EP51
MC10/100EP51
LVEL51
MC10EP51/D
tip 3055
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PDF
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tip 3055
Abstract: TSSOP-8
Text: MC10EP51, MC100EP51 3.3V / 5V ECL D Flip-Flop with Reset and Differential Clock Description The MC10/100EP51 is a differential clock D flip−flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices. The reset input is an asynchronous, level triggered signal. Data
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Original
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MC10EP51,
MC100EP51
MC10/100EP51
LVEL51
MC10EP51/D
tip 3055
TSSOP-8
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PDF
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HEL16
Abstract: DEVICE MARKING CODE table onsemi marking marking code onsemi marking code onsemi Diode kel33 on semiconductor traceability marking soic HEL32 HEL12 HEL31 HEL05
Text: AND8002/D ECLinPS, ECLinPS Lite, ECLinPS Plus, ECLinPS MAX, and GigaComm Marking and Ordering Information Guide http://onsemi.com APPLICATION NOTE Prepared by: Paul Shockman ON Semiconductor HFPD Applications Engineer Introduction This application note describes the device markings and
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Original
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AND8002/D
HEL16
DEVICE MARKING CODE table
onsemi marking
marking code onsemi
marking code onsemi Diode
kel33
on semiconductor traceability marking soic
HEL32
HEL12 HEL31
HEL05
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PDF
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Untitled
Abstract: No abstract text available
Text: MC10EP51, MC100EP51 3.3V / 5V ECL D Flip-Flop with Reset and Differential Clock Description The MC10/100EP51 is a differential clock D flip−flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices. The reset input is an asynchronous, level triggered signal. Data
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Original
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MC10EP51,
MC100EP51
MC10/100EP51
LVEL51
MC10EP51/D
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PDF
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