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Catalog Datasheet	Type	Document Tags	PDF
vhdl code CRC Abstract: C704DD7B SP006 4C11DB7 CRC calculation XAPP209 XAPP562 d9862f10 CRC Series C0010203 Text: Application Note: Virtex Series and Virtex-II Family Configurable LocalLink CRC Reference Design R Author: Nanditha Jayarajan XAPP562 v1.1.1 April 20, 2007 Summary The Cyclic Redundancy Check (CRC) is a checksum technique for testing data reliability and	Original	XAPP562 SP006: vhdl code CRC C704DD7B SP006 4C11DB7 CRC calculation XAPP209 XAPP562 d9862f10 CRC Series C0010203	PDF
XAPP691 Abstract: LocalLink XAPP258 10939 RAM32X1D vhdl code CRC 32 RAM64X1D XAPP261 SP006 xilinx logicore fifo generator 6.2 Text: Application Note: Virtex-II and Virtex-II Pro Families R Parameterizable LocalLink FIFO Author: Wen Ying Wei, Dai Huang XAPP691 v1.0.1 May 10, 2007 Summary This application note describes the implementation of a parameterizable LocalLink FIFO, which is a First-In-First-Out memory queue with LocalLink interfaces on both sides. The LocalLink	Original	XAPP691 XAPP258: XAPP261: SP006: DS232: XAPP691 LocalLink XAPP258 10939 RAM32X1D vhdl code CRC 32 RAM64X1D XAPP261 SP006 xilinx logicore fifo generator 6.2	PDF
XAPP1043 Abstract: IP Performance Using the XPS LocalLink TEMAC in an Embedded Processor System microblaze ethernet Tcp1323Opts ML505 8942 embedded system projects microblaze locallink ML405 PPC405 Text: Application Note: Embedded Processing Measuring Treck TCP/IP Performance Using the XPS LocalLink TEMAC in an Embedded Processor System R XAPP1043 v1.0 October 9, 2008 Abstract Author: Doug Gibbs This application note illustrates how to measure the network performance of the XPS LocalLink Tri Mode Ethernet MAC (TEMAC) in an embedded processor system running the Treck	Original	XAPP1043 PPC405 ML405 ML505 XAPP1043 IP Performance Using the XPS LocalLink TEMAC in an Embedded Processor System microblaze ethernet Tcp1323Opts 8942 embedded system projects microblaze locallink ML405	PDF
x112 Abstract: LocalLink XAPP1126 UART16550 X11261 ML507 PLBV46 PPC440 PPC440MC PLB DDR2 with OPB Central DMA Text: Application Note: Embedded Processing Reference System: Designing an EDK Custom Peripheral with a LocalLink Interface R XAPP1126 v1.0 December 10, 2008 Abstract Author: James Lucero This application note discusses the designing of an EDK core with a LocalLink interface. The	Original	XAPP1126 x112 LocalLink XAPP1126 UART16550 X11261 ML507 PLBV46 PPC440 PPC440MC PLB DDR2 with OPB Central DMA	PDF
vhdl code CRC Abstract: vhdl code CRC 32 verilog code 3 bit CRC SP006 CRC64 polynomial CRC64 verilog code for digital calculator LocalLink verilog code for fibre channel vhdl code CRC32 Text: Virtex-5 CRC Wizard v1.2 DS589 October 10, 2007 Product Specification Introduction LogiCORE Facts The LogiCORE Cyclic Redundancy Check CRC Wizard provides a LocalLink wrapper for the CRC hard macro available in the Virtex™-5 LXT and SXT devices. The CRC Wizard can be customized to suit a wide	Original	DS589 SP006: UG189: UG196: DS100: vhdl code CRC vhdl code CRC 32 verilog code 3 bit CRC SP006 CRC64 polynomial CRC64 verilog code for digital calculator LocalLink verilog code for fibre channel vhdl code CRC32	PDF
X1129 Abstract: linux26 ML507 PPC440 PPC440MC UART16550 XAPP1126 XAPP1129 xps serial peripheral interface 0x40400000 Text: Application Note: Embedded Processing R XAPP1129 v1.0 May 5, 2009 Abstract Integrating an EDK Custom Peripheral with a LocalLink Interface into Linux Author: Brian Hill This application note discusses the usage of a Local Link DMA peripheral with the Linux	Original	XAPP1129 ML507 X1129 linux26 PPC440 PPC440MC UART16550 XAPP1126 XAPP1129 xps serial peripheral interface 0x40400000	PDF
DS504 Abstract: LocalLink Text: SPI-3 Link Layer v5.1 DS504 August 8, 2007 Product Specification Introduction LogiCORE Facts The Xilinx LogiCORE SPI-3 Link Layer core provides a complete, pre-engineered solution that is fully compatible with the OIF-SPI3-01.0 System Packet Interface Level-3 standard. Implementation Agreement. This	Original	DS504 OIF-SPI3-01 LocalLink	PDF
verilog code for fibre channel Abstract: DS518 RXRECCLK PPC405 xilinx 9.1i verilog code fc 2 vhdl code for frame synchronization xilinx logicore fifo generator vhdl code for loop verilog code for frame synchronization Text: Fibre Channel Arbitrated Loop v2.2 DS518 August 8, 2007 Product Specification Introduction LogiCORE Facts The LogiCORE Fibre Channel Arbitrated Loop FC-AL core provides a flexible, fully verified solution for use in any FC-AL port design. The core handles all link initialization and loop arbitration functions and includes credit	Original	DS518 verilog code for fibre channel RXRECCLK PPC405 xilinx 9.1i verilog code fc 2 vhdl code for frame synchronization xilinx logicore fifo generator vhdl code for loop verilog code for frame synchronization	PDF
XC3S500E Abstract: reliability report of nxp PX1011A PX1011A-EL1 DO-DI-PCIEXP "network interface cards" Text: 11 Endpoint PIPE v1.7 for PCI Express DS321 May 17, 2007 Product Specification Introduction LogiCORE Facts The Endpoint PIPE PHY Interface for PCI Express 1-lane core is a high-bandwidth scalable and reliable serial interconnect intellectual property building block	Original	DS321 XC3S500E reliability report of nxp PX1011A PX1011A-EL1 DO-DI-PCIEXP "network interface cards"	PDF
vhdl source code for i2c optic Abstract: DS543 microblaze locallink Text: MOST Network Interface Controller v1.2 DS543 August 8, 2007 Product Specification Introduction LogiCORE Facts The LogiCORE Media Oriented Systems Transport Network Interface Controller MOST NIC core is a complete controller designed to the MOST Specification	Original	DS543 25nse vhdl source code for i2c optic microblaze locallink	PDF
8e1111 Abstract: Marvell PHY 88E1111 ml505 Marvell PHY 88E1111 Datasheet microblaze ethernet ML505 ML507 sgmii 88E1111 Marvell PHY 88E1111 Xilinx XAPP957 88E1111 and SFP applications Text: Application Note: Virtex-5 Embedded Tri-Mode Ethernet Core R Virtex-5 Embedded Tri-Mode Ethernet MAC Hardware Demonstration Platform XAPP957 v1.1 October 8, 2008 Summary This application note describes a system using the Virtex -5 Embedded Tri-Mode Ethernet	Original	XAPP957 ML505 ML507development ML507: ml507 xapp957 UG170, UG194, UG347, 8e1111 Marvell PHY 88E1111 ml505 Marvell PHY 88E1111 Datasheet microblaze ethernet sgmii 88E1111 Marvell PHY 88E1111 Xilinx 88E1111 and SFP applications	PDF
MP21608S221A Abstract: UG198 FERRITE-220 GTX tile oversampling recovered clock ROSENBERGER verilog code for linear interpolation filter aurora GTX BLM15HB221SN1 gearbox rev maxim DVB Text: Virtex-5 FPGA RocketIO GTX Transceiver User Guide UG198 v2.1 November 17, 2008 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the	Original	UG198 MP21608S221A UG198 FERRITE-220 GTX tile oversampling recovered clock ROSENBERGER verilog code for linear interpolation filter aurora GTX BLM15HB221SN1 gearbox rev maxim DVB	PDF
ug196 Abstract: johnson tiles GTX tile oversampling recovered clock XC5VLX30T-FF323 aurora GTX ROSENBERGER XC5VSX50TFF665 2F-15 UCF virtex-4 BLM15HB221SN1 Text: Virtex-5 FPGA RocketIO GTP Transceiver User Guide UG196 v2.0 June 10, 2009 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the	Original	UG196 ug196 johnson tiles GTX tile oversampling recovered clock XC5VLX30T-FF323 aurora GTX ROSENBERGER XC5VSX50TFF665 2F-15 UCF virtex-4 BLM15HB221SN1	PDF
jesd79f Abstract: UG388 MT41J256M8xx-187E 8 XC6SLX9 MT41J256M8xx-187E ddr3 ram slot pin detail MT41J64M16xx-187E micron DDR3 pcb layout MT41K128M8 Spartan-6 LX45 Text: Spartan-6 FPGA Memory Controller User Guide UG388 v2.3 August 9, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the	Original	UG388 com/pdf/technotes/ddr2/TN4708 com/pdf/technotes/ddr2/TN4720 TMS320C6454/5 jesd79f UG388 MT41J256M8xx-187E 8 XC6SLX9 MT41J256M8xx-187E ddr3 ram slot pin detail MT41J64M16xx-187E micron DDR3 pcb layout MT41K128M8 Spartan-6 LX45	PDF

virtex-6 ML605 user guide Abstract: UG353 vhdl code 8 bit LFSR ML605 UCF FILE virtex 5 fpga utilization simple 32 bit LFSR using verilog 65Gbps SP006 virtex-5 ML605 user guide aurora GTX Text: LogiCORE IP Aurora 8B/10B v5.3 DS637 January 18, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP Aurora 8B/10B core implements the Aurora 8B/10B protocol using the high-speed serial transceivers on the Virtex -5 LXT, SXT, FXT, and TXT	Original	8B/10B DS637 virtex-6 ML605 user guide UG353 vhdl code 8 bit LFSR ML605 UCF FILE virtex 5 fpga utilization simple 32 bit LFSR using verilog 65Gbps SP006 virtex-5 ML605 user guide aurora GTX	PDF
DS509 Abstract: SD10 SD12 SD13 2V220 binaryencoded Text: - DISCONTINUED PRODUCT Packet Queue v2.2 DS509 August 8, 2007 Product Specification Introduction The Xilinx LogiCORE Packet Queue is ideal for systems that require buffering packet-based data from multiple input streams with aggregation into a single output interface. Packet Queue implements a fully	Original	DS509 SD10 SD12 SD13 2V220 binaryencoded	PDF
example ml605 Abstract: Marvell PHY 88E1111 Xilinx ML605 example ml605 ethernet 88E1111 RGMII config Marvell PHY 88E1111 Xilinx spartan virtex-6 ML605 user guide Marvell PHY 88E1111 Xilinx ML605 microblaze ethernet virtex 5 ML605 Marvell PHY 88E1111 Datasheet Xilinx ML605 Text: Application Note: Virtex-6 Embedded Tri-Mode Ethernet MAC Virtex-6 Embedded Tri-Mode Ethernet MAC Hardware Demonstration Platform XAPP1144 v1.0 October 15, 2009 Summary This application note describes a system using the Virtex -6 Embedded Tri-Mode Ethernet	Original	XAPP1144 ML605 example ml605 Marvell PHY 88E1111 Xilinx example ml605 ethernet 88E1111 RGMII config Marvell PHY 88E1111 Xilinx spartan virtex-6 ML605 user guide Marvell PHY 88E1111 Xilinx ML605 microblaze ethernet virtex 5 ML605 Marvell PHY 88E1111 Datasheet Xilinx ML605	PDF
Untitled Abstract: No abstract text available Text: LogiCORE IP Multi-Port Memory Controller v6.06.a DS643 February 22, 2013 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP Multi-Port Memory Controller (MPMC) is a fully parameterizable memory controller that supports SDRAM/DDR/DDR2/DDR3/LPDDR	Original	DS643 PPC440MC)	PDF
picoblaze Abstract: microblaze ethernet microblaze ethernet lite microblaze Embedded Processing microblaze locallink SPARTAN-3 XC3S400 uclinux xc3s100 XAPP477 Text: Application Note: Spartan-3 FPGA Family R Embedded Processing and Control Solutions for Spartan-3 FPGAs XAPP477 v1.0.1 August 11, 2003 Introduction In a variety of applications, an embedded processor or controller is key to system flexibility, maintainability, and low cost. Spartan-3 FPGAs support two powerful yet flexible Field	Original	XAPP477 32-bit picoblaze microblaze ethernet microblaze ethernet lite microblaze Embedded Processing microblaze locallink SPARTAN-3 XC3S400 uclinux xc3s100 XAPP477	PDF
XAPP477 Abstract: picoblaze Xilinx Parallel Cable IV spartan-3 XC3S400 uart microblaze ethernet lite microblaze SPARTAN 6 peripherals XC3S400 FPGAs Embedded Processing xilinx spartan xc3s400 Text: Application Note: Spartan-3 FPGA Family R Embedded Processing and Control Solutions for Spartan-3 FPGAs XAPP477 v1.0.1 August 11, 2003 Introduction In a variety of applications, an embedded processor or controller is key to system flexibility, maintainability, and low cost. Spartan-3 FPGAs support two powerful yet flexible Field	Original	XAPP477 32-bit XAPP477 picoblaze Xilinx Parallel Cable IV spartan-3 XC3S400 uart microblaze ethernet lite microblaze SPARTAN 6 peripherals XC3S400 FPGAs Embedded Processing xilinx spartan xc3s400	PDF
UG196 Abstract: MP21608S221A xc5vlx30t-ff323 XC5VLX155T-FF1738 XC5VSX50TFF665 direct sequence spread spectrum virtex-5 FERRITE-220 FF1136 XC5VLX30T-FF665 XC5VLX110T-FF1738 Text: Virtex-5 FPGA RocketIO GTP Transceiver User Guide UG196 v2.1 December 3, 2009 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the	Original	UG196 time16 UG196 MP21608S221A xc5vlx30t-ff323 XC5VLX155T-FF1738 XC5VSX50TFF665 direct sequence spread spectrum virtex-5 FERRITE-220 FF1136 XC5VLX30T-FF665 XC5VLX110T-FF1738	PDF
vhdl code for DES algorithm Abstract: XAPP921c FLOATING POINT PROCESSOR TMSC6000 pulse compression radar fir filter matlab code LMS adaptive filter simulink model verilog code for lms adaptive equalizer for audio LMS simulink 3SD1800A XILINX vhdl code REED SOLOMON encoder decoder fir filter with lms algorithm in vhdl code Text: XtremeDSP Solutions Selection Guide June 2008 Introduction Contents DSP System Solutions.4 DSP Devices.17 Development Tools.25 Complementary Solutions.33 Resources.35	Original		PDF
manual SPARTAN-3 XC3S400 evaluation kit Abstract: hcl l21 usb power supply circuit diagram verilog code for Modified Booth algorithm vhdl code for lcd of spartan3E UG331 TT 2222 Horizontal Output Transistor pins out dia verilog for 8 point fft using FPGA spartan3 vhdl code for ldpc decoder types of multipliers ge fanuc cpu 331 Text: Spartan-3 Generation FPGA User Guide Extended Spartan-3A, Spartan-3E, and Spartan-3 FPGA Families UG331 v1.7 August 19, 2010 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development	Original	UG331 guides/ug332 manual SPARTAN-3 XC3S400 evaluation kit hcl l21 usb power supply circuit diagram verilog code for Modified Booth algorithm vhdl code for lcd of spartan3E UG331 TT 2222 Horizontal Output Transistor pins out dia verilog for 8 point fft using FPGA spartan3 vhdl code for ldpc decoder types of multipliers ge fanuc cpu 331	PDF
XILINX ipic Abstract: full bridge IPIF asynchronous PAR64 PCI32 REQ64 SG28c Virtex-4 User Guide Text: PLB PCI Full Bridge v1.00a DS508 March 21, 2006 Product Specification Introduction LogiCORE Facts Supported Device Family Virtex™-II Pro, Virtex-4 plb_pci Resources Used Virtex-IIP Min Max 49 50 I/O (PLB-related) 397 433 LUTs 3350 3870 2570 2970 8 8	Original	DS508 32-bit/33 64-Bit XILINX ipic full bridge IPIF asynchronous PAR64 PCI32 REQ64 SG28c Virtex-4 User Guide	PDF

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LOCALLINK Datasheets Context Search

vhdl code CRC

XAPP691

XAPP1043

x112

vhdl code CRC

X1129

DS504

verilog code for fibre channel

XC3S500E

vhdl source code for i2c optic

8e1111

MP21608S221A

ug196

jesd79f

virtex-6 ML605 user guide

DS509

example ml605

Untitled

picoblaze

XAPP477

UG196

vhdl code for DES algorithm

manual SPARTAN-3 XC3S400 evaluation kit

XILINX ipic