G12-l
Abstract: LSI Logic ASIC g12 High Voltage G12L g12 transistor G12 000
Text: G12 ASIC Cell-Based Product Features/ Benefits Twelfth Generation ASIC Technology • ASIC technology with 0.18 micron L-drawn Overview LSI Logic’s G12 ASIC Cell-Based product, with its three digital libraries, offers unprecedented options for system ASIC designers to optimize their ASIC or
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18-micron
13-micron
B20023
G12-l
LSI Logic ASIC g12
High Voltage G12L
g12 transistor
G12 000
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mdu 2653
Abstract: mdu 2654 BGA1152 transistor Arm 3055 equivalent Gigablaze serdes CMOS h27 j1 3003 RC1800 A207 resistor R10 J 2995 FC1152
Text: DATASHEET RapidChip Integrator Platform ASIC Family February 2005 Preliminary DB08-000237-03 This document is preliminary. As such, it contains data derived from functional simulations and performance estimates. LSI Logic has not verified either the
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DB08-000237-03
DB08-000237-03,
1152-Ball
mdu 2653
mdu 2654
BGA1152
transistor Arm 3055 equivalent
Gigablaze serdes CMOS
h27 j1 3003
RC1800
A207
resistor R10 J 2995
FC1152
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ddr phy
Abstract: DDR PHY ASIC LSI Rapidchip CW000722 CW761041 g12 DDR lsi CW761030
Text: RapidReady DDR-1 SDRAM Physical Layer Core CW761041 & CW000722 OVERVIEW FEATURES LSI Logic’s DDR-I physical layer core (PHY core) provides an integrationfriendly physical layer interface between the memory controller logic of the ASIC and the data and address busses of DDR-I SDRAM memory (see Figure1).
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CW761041
CW000722)
CW761041
18-micron
CW000722
C20057
ddr phy
DDR PHY ASIC
LSI Rapidchip
g12 DDR lsi
CW761030
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LVTTL18
Abstract: LSI Rapidchip epbga DB06-000160-04 DB06-000471-01
Text: DATASHEET Entry-Level RapidChip Platform ASIC Slices RC1812, RC18Si150, RC18Si184 October 2005 Advance ® DB08-000300-00 This document is advance. As such, it describes a product under development. This information is intended to help you evaluate the product. LSI Logic reserves
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RC1812,
RC18Si150,
RC18Si184
DB08-000300-00
DB08-000300-00,
EBG512,
LVTTL18
LSI Rapidchip
epbga
DB06-000160-04
DB06-000471-01
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ba05 regulator
Abstract: transistor code ak31 transistor BA29 AU04 3M RC7301 ba05 hp invent j04 RC1800 LSI Rapidchip 2aw22
Text: DATASHEET RC79301 StreamSlice Platform ASIC July 2003 Preliminary DB08-000235-00 This document is preliminary. As such, it contains data derived from functional simulations and performance estimates. LSI Logic has not verified either the functional descriptions, or the electrical and mechanical specifications using
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RC79301
DB08-000235-00
DB08-000235-00,
RC79301
responsib75
ba05 regulator
transistor code ak31
transistor BA29
AU04 3M
RC7301
ba05
hp invent j04
RC1800
LSI Rapidchip
2aw22
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IB39
Abstract: ATA100 ATA-100 29736
Text: G12 -p ATA100 3.3 V, 5-Volt Tolerant, Fail-Safe I/O Buffer Datasheet The ATA100 I/O buffer provides on-chip input/output I/O signaling for application-specific integrated circuit (ASIC) chips implemented in the LSI Logic G12™-p 0.13 µm process technology. The buffer operates at
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G12TM-p
ATA100
ATA100
ata100f5fsls33
atabiasls33
atacornerls33
atapvddio33
IB39
ATA-100
29736
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LSI LOGIC
Abstract: v 4520 lsi level translation
Text: G12 -p bd4f5fs60ls33 4 mA, 60 MHz, 5-Volt Tolerant, Fail-Safe I/O Buffer Datasheet The bd4f5fs60ls33 bidirectional buffer cell Figure 1 provides up to 60 MHz off-chip input/output (I/O) signaling for application-specific integrated circuit (ASIC) chips implemented in the LSI Logic G12™-p
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G12TM-p
bd4f5fs60ls33
bd4f5fs60ls33
G12TM-p
I15044
DB08-000160-00
LSI LOGIC
v 4520
lsi level translation
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a103 636 transistor
Abstract: MIPS32 cache LSI Rapidchip K9CFG CFG102 ARM926 ARM926EJ-S DB04-000094-02 Preliminary Gflx-r RapidChip Cell Technology Data infiniband PHY
Text: DATASHEET RapidChip Integrator Platform ASIC Family July 2004 Preliminary DB08-000237-02 This document is preliminary. As such, it contains data derived from functional simulations and performance estimates. LSI Logic has not verified either the functional descriptions, or the electrical and mechanical specifications using
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DB08-000237-02
DB08-000237-02,
a103 636 transistor
MIPS32 cache
LSI Rapidchip
K9CFG
CFG102
ARM926
ARM926EJ-S
DB04-000094-02
Preliminary Gflx-r RapidChip Cell Technology Data
infiniband PHY
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736-Pin
Abstract: LSI coreware library 64X144
Text: ADVANCE DATASHEET RC1800 Foundation Slice Family July 2005 The RapidChip RC1800 Foundation Platform ASIC Family, except for the RC1812 slice, is in NO-NEW-DESIGN Status as of July 2005. LSI Logic is not accepting new designs in this slice Family. Information in this datasheet is
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RC1800
RC1812
DB14-000253-04
DB14-000253-04,
DB14-000253-03
736-Pin
LSI coreware library
64X144
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lsi gigablaze transceiver
Abstract: LVTTL25
Text: DATASHEET RC11XT531 RapidChip Platform ASIC December 2003 Advance DB08-000236-01 This document is advance. As such, it describes a product under development. This information is intended to help you evaluate the product. LSI Logic reserves the right to change or discontinue this proposed product without notice.
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RC11XT531
DB08-000236-01
DB08-000236-01,
DB08-000236-01
lsi gigablaze transceiver
LVTTL25
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gigablaze
Abstract: 11-G02 TRANSISTOR A98 0.18-um CMOS technology multiplexer data sheet LSI gigablaze LSI gigablaze serdes MIPS32 RC11XT404 lsi asic databook RC11XT432
Text: ADVANCE DATASHEET RapidChip Xtreme Platform ASIC Family July 2004 DB08-000245-00 This document is advance. As such, it describes a product under development. This information is intended to help you evaluate the product. LSI Logic reserves the right to change or discontinue this proposed product without notice.
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DB08-000245-00
DB08-000245-00,
672-Ball
896-Ball
gigablaze
11-G02
TRANSISTOR A98
0.18-um CMOS technology multiplexer data sheet
LSI gigablaze
LSI gigablaze serdes
MIPS32
RC11XT404
lsi asic databook
RC11XT432
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IB14
Abstract: timing circuit 4536 4536 circuits 29736
Text: G12 -p Ultra160 SCSI Transceiver, 160 Mbytes/s SCSI Bus Transfer Rate Datasheet The Ultra160 SCSI1 transceiver and associated cells provide up to 160 Mbytes/s of on-chip input/output I/O signaling for application-specific integrated circuit (ASIC) chips implemented in the
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G12TM-p
Ultra160
scsiulvdls33
scsibiasls33
ddrvscsi5ls33
IB14
timing circuit 4536
4536 circuits
29736
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LSI Logic
Abstract: I1-5043
Text: G12 -p 3.3 V, 4 mA, 5-Volt Tolerant, Fail-Safe, General Purpose I/O Buffers Datasheet LSI Logic Corporation provides the following driver/receiver input/output I/O cells for use as general purpose I/O buffers: • bd4f5fsls33 • bd4puodf5fsls33 • bd4puf5fsls33
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G12TM-p
bd4f5fsls33
bd4puodf5fsls33
bd4puf5fsls33
bd4puodf5fscls33
I15043
DB08-000158-00
LSI Logic
I1-5043
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ARMv5TEJ
Abstract: ARM7EJ-S ARMv5T jazelle ARMv5 ARM processors LSI coreware library
Text: FlexCore ARM7EJ-S 32-bit Processor Core with Java™ acceleration OVERVIEW FEATURES AND BENEFITS LSI Logic offers FlexCore ARM7EJ-S processor cores available on both our Gflx™ 0.11 micron drawn and G12™ 0.18 micron (drawn) high performance process technologies, and configured to individual customer needs.
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32-bit
G12TM
ARMv5TEJ
ARM7EJ-S
ARMv5T
jazelle
ARMv5
ARM processors
LSI coreware library
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ARMv5TE instruction set
Abstract: ARM946E-S ARM9E-S ARMv5TE arm9e ARM946 ARMv5
Text: FlexCore ARM946E-S RISC Processor Cores TM 32-bit OVERVIEW FEATURES AND BENEFITS LSI Logic offers FlexCore ARM946E-S processor cores available on both our Gflx 0.11 micron drawn and G12™ 0.18 micron (drawn) high performance process technologies, fully configured to individual customer needs.
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ARM946E-S
32-bit
ARM946E-S
G12TM
ARMv5TE instruction set
ARM9E-S
ARMv5TE
arm9e
ARM946
ARMv5
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ARMv5TE
Abstract: ARMv5TE instruction set ARM966E-S ARMv5 ARM9E-STM
Text: FlexCore ARM966E-S 32-bit RISC Processor Cores OVERVIEW FEATURES AND BENEFITS LSI Logic offers FlexCore ARM966E-S processor cores available on both our Gflx 0.11 micron drawn and G12™ 0.18 micron (drawn) high performance process technologies, fully configured to individual customer needs.
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ARM966E-S
32-bit
G12TM
ARMv5TE
ARMv5TE instruction set
ARMv5
ARM9E-STM
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AMBA APB UART
Abstract: LSI LOGIC ARM7TDMI-S Datasheet CW001009 ARM7TDMI-S processor LSI Logic Corporation asic design flow amba bus architecture
Text: CW001009 - Low Power ARM7TDMI-S Synthesized Processor Core OVERVIEW FEATURES AND BENEFITS The CW001009 core is a low power implementation of the ARM7TDMI-S microprocessor core, synthesized onto LSI Logic’s G12L 0.18 micron low leakage process technology. The ARM7TDMI-S, licensed from ARM Limited, is
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CW001009
32-bit
16-bit
C20045
AMBA APB UART
LSI LOGIC
ARM7TDMI-S Datasheet
ARM7TDMI-S processor
LSI Logic Corporation
asic design flow
amba bus architecture
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ARM7TDMI-S
Abstract: LSI LOGIC ARM7TDMI-S Datasheet CW001010 AMBA APB UART
Text: CW001010 - 100 MHz ARM7TDMI-S Synthesized Processor Core OVERVIEW FEATURES AND BENEFITS The CW001010 core is a 100 MHz implementation of the ARM7TDMI-S microprocessor core, synthesized onto LSI Logic’s G12P 0.18 micron high performance process technology. The ARM7TDMI-S, licensed from ARM Limited,
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CW001010
32-bit
16-bit
C20048
ARM7TDMI-S
LSI LOGIC
ARM7TDMI-S Datasheet
AMBA APB UART
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design flow soc architecture
Abstract: ARM processor data flow ARM9E-S ARM9E-STM ARM966E-S CW001105 ARMv5TE instruction set ARMv5TE LSI cell library
Text: CW001105 - 200 MHz Synthesized ARM966E-S Core OVERVIEW FEATURES AND BENEFITS The CW001105 processor core is a 200 MHz implementation of the popular ARM966E-S™, synthesized onto LSI Logic’s G12P 0.18 micron high performance process technology. • 200 MHz Operating frequency
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CW001105
ARM966E-S
ARM966E-STM,
ARM966E-S,
C20042
design flow soc architecture
ARM processor data flow
ARM9E-S
ARM9E-STM
ARMv5TE instruction set
ARMv5TE
LSI cell library
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ARMv5TE instruction set
Abstract: ARM946E-STM ARMv5TE ARM946E-S ARM processor data flow design flow soc architecture ARM966E-S CW001100 TCMS
Text: CW001100 - 200 MHz Synthesized ARM946E-S Core with Cache Memories OVERVIEW FEATURES AND BENEFITS The CW001100 processor core is a 200 MHz implementation of the popular ARM946E-S™, synthesized onto LSI Logic’s G12P 0.18 micron high performance process technology.
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CW001100
ARM946E-STM
ARM946E-STM,
ARM946E-S,
R20050
ARMv5TE instruction set
ARMv5TE
ARM946E-S
ARM processor data flow
design flow soc architecture
ARM966E-S
TCMS
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LCA500K
Abstract: LSI LOGIC Oak Frequency Control Transistors alternatives scan TTL johnson ring counter LCA50 logic diagram of johnson and ring counter
Text: An ASIC Primer Table of Contents Preface - Preface .0-1 Chapter 1 - What is an ASIC? .1-1 Section 1 - Uses of ASICs .1-1
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011U
Abstract: LSI coreware library ARM11 lsi logic ARM11 "instruction set summary" armv5te cp14 ARM coprocessor
Text: DATASHEET 0.11µ ARM966E-S Processor cw001163_1_0 October 2004 Preliminary DB08-000257-00 This document is preliminary. As such, it contains data derived from functional simulations and performance estimates. LSI Logic has not verified either the functional descriptions, or the electrical and mechanical specifications using
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ARM966E-STM
cw001163
DB08-000257-00
DB08-000257-00,
ARM966E-S
011U
LSI coreware library
ARM11 lsi logic
ARM11 "instruction set summary"
armv5te cp14
ARM coprocessor
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LSI coreware library
Abstract: LSI LOGIC OakDSPCore "Hot Plug and Play"
Text: USB Host Core Host Core for Universal Serial Bus Solutions Overview The USB Host Core, a component of LSI Logic’s comprehensive USB solution set, is a flexible and configurable core that manages and generates the Universal Serial Bus, providing support of USB peripherals in highly integrated embedded systems.
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ARM926EJ-S
Abstract: ARM926EJ-S Implementation Guide 011U LogicVision Preliminary Gflx-r RapidChip Cell Technology Data LSI Rapidchip cpdin ARM926EJ-S errata
Text: DATASHEET 0.11µ ARM926EJ-S Processor cw001124_1_0 October 2004 Preliminary DB08-000262-00 This document is preliminary. As such, it contains data derived from functional simulations and performance estimates. LSI Logic has not verified either the functional descriptions, or the electrical and mechanical specifications using
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ARM926EJ-STM
cw001124
DB08-000262-00
DB08-000262-00,
ARM926EJ-S
ARM926EJ-S Implementation Guide
011U
LogicVision
Preliminary Gflx-r RapidChip Cell Technology Data
LSI Rapidchip
cpdin
ARM926EJ-S errata
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