LVCH32501A Search Results

LVCH32501A Result Highlights (3)

Part	ECAD Model	Manufacturer	Description	Download	Buy
LVCH32501AU		Renesas Electronics Corporation	3.3V CMOS 36-BIT BUFF LAT
74LVCH32501ABF		Renesas Electronics Corporation	3.3V CMOS 36-BIT BUFF LAT
74LVCH32501ABF8		Renesas Electronics Corporation	3.3V CMOS 36-BIT BUFF LAT

LVCH32501A Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
IDT74LVCH32501A Abstract: LVCH32501A Text: LVCH32501A ADVANCE INFORMATION 3.3V CMOS 36-BIT REGISTERED TRANSCEIVER, 5 VOLT TOLERANT I/O, BUS-HOLD Integrated Device Technology, Inc. DESCRIPTION: FEATURES: This 36-bit registered transceiver is built using advanced dual metal CMOS technology. This device combines D-type	Original	IDT74LVCH32501A 36-BIT 36-bit 32-bit IDT74LVCH32501A LVCH32501A	PDF
IDT74LVCH32501A Abstract: LVCH32501A Text: LVCH32501A 3.3V CMOS 36-BIT REGISTERED TRANSCEIVER EXTENDED COMMERCIAL TEMPERATURE RANGE LVCH32501A 3.3V CMOS 36-BIT REGISTERED TRANSCEIVER WITH 5 VOLT TOLERANT I/O AND BUS-HOLD FEATURES: – – – – – – – – – DESCRIPTION: Typical tSK o (Output Skew) < 250ps	Original	IDT74LVCH32501A 36-BIT 36-BIT 250ps MIL-STD-883, 200pF, 32-bit IDT74LVCH32501A LVCH32501A	PDF
Untitled Abstract: No abstract text available Text: LVCH32501A 3.3V CMOS 36-BIT REGISTERED TRANSCEIVER WITH 5V TOLERANT I/O INDUSTRIAL TEMPERATURE RANGE LVCH32501A 3.3V CMOS 36-BIT REGISTERED TRANSCEIVER WITH 5 VOLT TOLERANT I/O AND BUS-HOLD FEATURES: DESCRIPTION: • Typical tSK o (Output Skew) < 250ps	Original	IDT74LVCH32501A 36-BIT 36-BIT 250ps MIL-STD-883, 200pF, 114-ball	PDF
Untitled Abstract: No abstract text available Text: LVCH32501A 3.3V CMOS 36-BIT REGISTERED TRANSCEIVER WITH 5V TOLERANT I/O INDUSTRIAL TEMPERATURE RANGE LVCH32501A 3.3V CMOS 36-BIT REGISTERED TRANSCEIVER WITH 5 VOLT TOLERANT I/O AND BUS-HOLD FEATURES: DESCRIPTION: • Typical tSK o (Output Skew) < 250ps	Original	IDT74LVCH32501A 36-BIT 250ps MIL-STD-883, 200pF, 114-ball IDT74LVCH32501A	PDF
Untitled Abstract: No abstract text available Text: 3.3V CMOS 36-BIT REGISTERED TRANSCEIVER, 5 VOLT TOLERANT I/O, BUS-HOLD DESCRIPTION: FEATURES: - This 3 6-bit registered tran sceive r is built using advanced dual m etal C M O S technology. This device com bines D-type latches and D -type flip-flops to allow d ata flow in transparent,	OCR Scan	36-BIT 250ps 200pF, IDT74LVCH32501A	PDF
Untitled Abstract: No abstract text available Text: 3.3V CMOS 36-BIT REGISTERED TRANSCEIVER, 5 VOLT TOLERANT I/O, BUS-HOLD DESCRIPTION: FEATURES: - This 36-bit registered transceiver is built using advanced dual metal CMOS technology. This device combines D-type latches and D-type flip-flops to allow data flow in transparent,	OCR Scan	36-BIT 250ps MIL-STD-883, 200pF, IDT74LVCH32501A	PDF