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    MARKING NXP TSSOP8 PACKAGE Search Results

    MARKING NXP TSSOP8 PACKAGE Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TPH9R00CQH Toshiba Electronic Devices & Storage Corporation MOSFET, N-ch, 150 V, 64 A, 0.009 Ohm@10V, SOP Advance / SOP Advance(N) Visit Toshiba Electronic Devices & Storage Corporation
    TPH2R408QM Toshiba Electronic Devices & Storage Corporation MOSFET, N-ch, 80 V, 120 A, 0.00243 Ohm@10V, SOP Advance Visit Toshiba Electronic Devices & Storage Corporation
    XPH2R106NC Toshiba Electronic Devices & Storage Corporation N-ch MOSFET, 60 V, 110 A, 0.0021 Ω@10V, SOP Advance(WF) Visit Toshiba Electronic Devices & Storage Corporation
    XPH3R206NC Toshiba Electronic Devices & Storage Corporation N-ch MOSFET, 60 V, 70 A, 0.0032 Ω@10V, SOP Advance(WF) Visit Toshiba Electronic Devices & Storage Corporation
    TPH4R008QM Toshiba Electronic Devices & Storage Corporation MOSFET, N-ch, 80 V, 86 A, 0.004 Ohm@10V, SOP Advance(N) Visit Toshiba Electronic Devices & Storage Corporation

    MARKING NXP TSSOP8 PACKAGE Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    NXP G2XM EPC

    Abstract: G2XM NXP EPC UCODE G2X NXP UCODE G2XM J122 transistor SOT1040AB2 SL3S1002FTT sot1122 SL3S1202FTB1 SOT-1122
    Text: SL3ICS1002/1202 UCODE G2XM and G2XL Rev. 3.5 — 2 November 2009 157335 Product short data sheet CONFIDENTIAL 1. General description The UHF EPCglobal Generation 2 standard allows the commercialized provision of mass adoption of UHF RFID technology for passive smart tags and labels. Main fields of


    Original     		PDF SL3ICS1002/1202 NXP G2XM EPC G2XM NXP EPC UCODE G2X NXP UCODE G2XM J122 transistor SOT1040AB2 SL3S1002FTT sot1122 SL3S1202FTB1 SOT-1122

    74LVC2G32

    Abstract: 74LVC2G32DC 74LVC2G32DP 74LVC2G32GM 74LVC2G32GT MO-187 VSSOP8
    Text: 74LVC2G32 Dual 2-input OR gate Rev. 06 — 27 February 2008 Product data sheet 1. General description The 74LVC2G32 provides a 2-input OR gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.


    Original     		PDF 74LVC2G32 74LVC2G32 74LVC2G32DC 74LVC2G32DP 74LVC2G32GM 74LVC2G32GT MO-187 VSSOP8

    74AHC2G08

    Abstract: 74AHC2G08DC 74AHC2G08DP 74AHCT2G08 74AHCT2G08DC 74AHCT2G08DP JESD22-A114E
    Text: 74AHC2G08; 74AHCT2G08 Dual 2-input AND gate Rev. 03 — 12 January 2009 Product data sheet 1. General description The 74AHC2G08; 74AHCT2G08 is a high-speed Si-gate CMOS device. The 74AHC2G08; 74AHCT2G08 provides two 2-input AND gates. 2. Features • Symmetrical output impedance


    Original     		PDF 74AHC2G08; 74AHCT2G08 74AHCT2G08 JESD22-A114E JESD22-A115-A JESD22-C101C 74AHC2G08DP 74AHC2G08 74AHC2G08DC 74AHC2G08DP 74AHCT2G08DC 74AHCT2G08DP

    74HC3G04DP

    Abstract: 74HC3G04 74HC3G04DC 74HC3G04GD 74HCT3G04 74HCT3G04DC 74HCT3G04DP 74HCT3G04GD JESD22-A114E
    Text: 74HC3G04; 74HCT3G04 Inverter Rev. 03 — 2 July 2008 Product data sheet 1. General description The 74HC3G04 and 74HCT3G04 are high-speed Si-gate CMOS devices. They provide three inverting buffers. The HC device has CMOS input switching levels and supply voltage range 2 V to 6 V.


    Original     		PDF 74HC3G04; 74HCT3G04 74HC3G04 74HCT3G04 JESD22-A114E JESD22-A115-A HCT3G04 74HC3G04DP 74HC3G04DC 74HC3G04GD 74HCT3G04DC 74HCT3G04DP 74HCT3G04GD

    74HC2G32

    Abstract: 74HC2G32DC 74HC2G32DP 74HCT2G32 74HCT2G32DC 74HCT2G32DP JESD22-A114E
    Text: 74HC2G32; 74HCT2G32 Dual 2-input OR gate Rev. 03 — 12 May 2009 Product data sheet 1. General description The 74HC2G32 and 74HCT2G32 are high-speed Si-gate CMOS devices. They provide two 2-input OR gates. The HC device has CMOS input switching levels and supply voltage range 2 V to 6 V.


    Original     		PDF 74HC2G32; 74HCT2G32 74HC2G32 74HCT2G32 JESD22-A114E JESD22-A115-A HCT2G32 74HC2G32DC 74HC2G32DP 74HCT2G32DC 74HCT2G32DP

    74AHC3G04

    Abstract: 74AHC3G04DC 74AHC3G04DP 74AHCT3G04 74AHCT3G04DC 74AHCT3G04DP JESD22-A114E
    Text: 74AHC3G04; 74AHCT3G04 Inverter Rev. 02 — 26 January 2009 Product data sheet 1. General description The 74AHC3G04; 74AHCT3G04 is a high-speed Si-gate CMOS device. The 74AHC3G04; 74AHCT3G04 provides three inverting buffers. 2. Features • Symmetrical output impedance


    Original     		PDF 74AHC3G04; 74AHCT3G04 74AHCT3G04 JESD22-A114E JESD22-A115-A JESD22-C101C 74AHC3G04DP 74AHC3G04 74AHC3G04DC 74AHC3G04DP 74AHCT3G04DC 74AHCT3G04DP

    74HCT2G125DP

    Abstract: 74HC125 74HC2G125 74HC2G125DC 74HC2G125DP 74HCT125 74HCT2G125 74HCT2G125DC JESD22-A114E VSSOP8
    Text: 74HC2G125; 74HCT2G125 Dual buffer/line driver; 3-state Rev. 04 — 4 July 2008 Product data sheet 1. General description The 74HC2G125; 74HCT2G125 is a high-speed, Si-gate CMOS device. The 74HC2G125; 74HCT2G125 provides two non-inverting buffer/line drivers with 3-state


    Original     		PDF 74HC2G125; 74HCT2G125 74HCT2G125 74HC125 74HCT125. JESD22-A114E HCT2G125 74HCT2G125DP 74HC2G125 74HC2G125DC 74HC2G125DP 74HCT125 74HCT2G125DC VSSOP8

    SOT996-2

    Abstract: 74AHC2G00 74AHC2G00DC 74AHC2G00DP 74AHCT2G00 74AHCT2G00DC 74AHCT2G00DP JESD22-A114E
    Text: 74AHC2G00; 74AHCT2G00 Dual 2-input NAND gate Rev. 02 — 12 January 2009 Product data sheet 1. General description The 74AHC2G00; 74AHCT2G00 is a high-speed Si-gate CMOS device. The 74AHC2G00; 74AHCT2G00 provides two 2-input NAND gates. 2. Features • Symmetrical output impedance


    Original     		PDF 74AHC2G00; 74AHCT2G00 74AHCT2G00 JESD22-A114E JESD22-A115-A JESD22-C101C 74AHC2G00DP SOT996-2 74AHC2G00 74AHC2G00DC 74AHC2G00DP 74AHCT2G00DC 74AHCT2G00DP

    VSSOP8

    Abstract: 74HC3GU04 74HC3GU04DC 74HC3GU04DP JESD22-A114E MO-187
    Text: 74HC3GU04 Inverter Rev. 03 — 11 May 2009 Product data sheet 1. General description The 74HC3GU04 is a high-speed Si-gate CMOS device. This device provides three inverter gates with unbuffered outputs. The 74HC3GU04 has CMOS input switching levels and supply voltage range 2 V to 6 V.


    Original     		PDF 74HC3GU04 74HC3GU04 JESD22-A114E JESD22-A115-A VSSOP8 74HC3GU04DC 74HC3GU04DP MO-187

    74AHC3GU04

    Abstract: 74AHC3GU04DC 74AHC3GU04DP 74AHC3GU04GM JESD22-A114E MO-187
    Text: 74AHC3GU04 Inverter Rev. 03 — 26 January 2009 Product data sheet 1. General description The 74AHC3GU04 is a high-speed Si-gate CMOS device. This device provides the inverting single stage function. 2. Features • Symmetrical output impedance ■ High noise immunity


    Original     		PDF 74AHC3GU04 74AHC3GU04 JESD22-A114E JESD22-A115-A JESD22-C101C 74AHC3GU04DP 74AHC3GU04DC 74AHC3GU04DP 74AHC3GU04GM MO-187

    74LVC3G14

    Abstract: 74LVC3G14DC 74LVC3G14DP 74LVC3G14GM 74LVC3G14GT JESD22-A114E MO-187
    Text: 74LVC3G14 Triple inverting Schmitt trigger with 5 V tolerant input Rev. 07 — 12 June 2008 Product data sheet 1. General description The 74LVC3G14 provides three inverting buffers with Schmitt trigger action. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of


    Original     		PDF 74LVC3G14 74LVC3G14 74LVC3G14DC 74LVC3G14DP 74LVC3G14GM 74LVC3G14GT JESD22-A114E MO-187

    74HC2G08DP

    Abstract: 74HC2G08 74HC2G08DC 74HCT2G08 74HCT2G08DC 74HCT2G08DP JESD22-A114E
    Text: 74HC2G08; 74HCT2G08 Dual 2-input AND gate Rev. 04 — 7 May 2009 Product data sheet 1. General description The 74HC2G08 and 74HCT2G08 are high-speed Si-gate CMOS devices. They provide two 2-input AND gates. The HC device has CMOS input switching levels and supply voltage range 2 V to 6 V.


    Original     		PDF 74HC2G08; 74HCT2G08 74HC2G08 74HCT2G08 JESD22-A114E JESD22-A115-A HCT2G08 74HC2G08DP 74HC2G08DC 74HCT2G08DC 74HCT2G08DP

    74AHC3G14

    Abstract: 74AHC3G14DC 74AHC3G14DP 74AHC3G14GD 74AHCT3G14 74AHCT3G14DC 74AHCT3G14DP JESD22-A114E AHC* marking
    Text: 74AHC3G14; 74AHCT3G14 Inverting Schmitt trigger Rev. 04 — 5 May 2009 Product data sheet 1. General description 74AHC3G14 and 74AHCT3G14 are high-speed Si-gate CMOS devices. They provide an inverting buffer function with Schmitt trigger action. These devices are capable of


    Original     		PDF 74AHC3G14; 74AHCT3G14 74AHC3G14 74AHCT3G14 JESD22-A114E JESD22-A115-A JESD22-C101C AHCT3G14 74AHC3G14DC 74AHC3G14DP 74AHC3G14GD 74AHCT3G14DC 74AHCT3G14DP AHC* marking

    74*06

    Abstract: h06 diode marking h06 74HC3G06 74HC3G06DC 74HC3G06DP 74HCT3G06 74HCT3G06DC 74HCT3G06DP JESD22-A114E
    Text: 74HC3G06; 74HCT3G06 Triple inverter with open-drain outputs Rev. 03 — 11 May 2009 Product data sheet 1. General description The 74HC3G06 and 74HCT3G06 are high-speed Si-gate CMOS devices. They provide three inverting buffers with open-drain outputs. The outputs of the 74HC3G06 and 74HCT3G06 devices are open drains and can be


    Original     		PDF 74HC3G06; 74HCT3G06 74HC3G06 74HCT3G06 HCT3G06 74*06 h06 diode marking h06 74HC3G06DC 74HC3G06DP 74HCT3G06DC 74HCT3G06DP JESD22-A114E

    74LVC3GU04

    Abstract: 74LVC3GU04DC 74LVC3GU04DP 74LVC3GU04GM 74LVC3GU04GT JESD22-A114E MO-187 VU04
    Text: 74LVC3GU04 Triple inverter Rev. 06 — 4 March 2008 Product data sheet 1. General description The 74LVC3GU04 provides three inverters. Each inverter is a single stage with unbuffered output. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of


    Original     		PDF 74LVC3GU04 74LVC3GU04 JESD8B/JESD36 JESD22-A114E JESD22-A115-A 74LVC3GU04DC 74LVC3GU04DP 74LVC3GU04GM 74LVC3GU04GT MO-187 VU04

    74LVC2G86

    Abstract: 74LVC2G86DC 74LVC2G86DP 74LVC2G86GM 74LVC2G86GT JESD22-A114E MO-187
    Text: 74LVC2G86 Dual 2-input EXCLUSIVE-OR gate Rev. 06 — 22 February 2008 Product data sheet 1. General description The 74LVC2G86 provides a dual 2-input EXCLUSIVE-OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these


    Original     		PDF 74LVC2G86 74LVC2G86 74LVC2G86DC 74LVC2G86DP 74LVC2G86GM 74LVC2G86GT JESD22-A114E MO-187

    74AHC2G126DP

    Abstract: AHC* marking 74AHC2G126 74AHC2G126DC 74AHCT2G126 74AHCT2G126DC 74AHCT2G126DP JESD22-A114E
    Text: 74AHC2G126; 74AHCT2G126 Dual buffer/line driver; 3-state Rev. 5 — 24 March 2011 Product data sheet 1. General description The 74AHC2G126 and 74AHCT2G126 are high-speed Si-gate CMOS devices. They provide a dual non-inverting buffer/line driver with 3-state output. The 3-state output is


    Original     		PDF 74AHC2G126; 74AHCT2G126 74AHC2G126 74AHCT2G126 AHCT2G126 74AHC2G126DP AHC* marking 74AHC2G126DC 74AHCT2G126DC 74AHCT2G126DP JESD22-A114E

    74HC3G14

    Abstract: 74HC3G14DC 74HC3G14DP 74HCT3G14 74HCT3G14DC 74HCT3G14DP JESD22-A114E
    Text: 74HC3G14; 74HCT3G14 Triple inverting Schmitt trigger Rev. 03 — 8 May 2009 Product data sheet 1. General description The 74HC3G14; 74HCT3G14 is a high-speed Si-gate CMOS device. The 74HC3G14; 74HCT3G14 provides three inverting buffers with Schmitt trigger inputs


    Original     		PDF 74HC3G14; 74HCT3G14 74HCT3G14 JESD22-A114E JESD22-A115-A HCT3G14 74HC3G14 74HC3G14DC 74HC3G14DP 74HCT3G14DC 74HCT3G14DP

    74LVC2G32

    Abstract: 74LVC2G32DC 74LVC2G32DP 74LVC2G32GM 74LVC2G32GT JESD22-A114E MO-187
    Text: 74LVC2G32 Dual 2-input OR gate Rev. 07 — 6 June 2008 Product data sheet 1. General description The 74LVC2G32 provides a 2-input OR gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.


    Original     		PDF 74LVC2G32 74LVC2G32 74LVC2G32DC 74LVC2G32DP 74LVC2G32GM 74LVC2G32GT JESD22-A114E MO-187

    74LVC3G06

    Abstract: 74LVC3G06DC 74LVC3G06DP 74LVC3G06GM 74LVC3G06GT JESD22-A114E MO-187
    Text: 74LVC3G06 Triple inverter with open-drain output Rev. 07 — 12 March 2009 Product data sheet 1. General description The 74LVC3G06 provides three inverting buffers. The output of this device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.


    Original     		PDF 74LVC3G06 74LVC3G06 74LVC3G06DC 74LVC3G06DP 74LVC3G06GM 74LVC3G06GT JESD22-A114E MO-187

    74LVC3G04

    Abstract: 74LVC3G04DC 74LVC3G04DP 74LVC3G04GM 74LVC3G04GT JESD22-A114E MO-187
    Text: 74LVC3G04 Triple inverter Rev. 07 — 16 June 2008 Product data sheet 1. General description The 74LVC3G04 provides three inverting buffers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.


    Original     		PDF 74LVC3G04 74LVC3G04 74LVC3G04DC 74LVC3G04DP 74LVC3G04GM 74LVC3G04GT JESD22-A114E MO-187

    v86 5-pin

    Abstract: 74LVC2G86 74LVC2G86DC 74LVC2G86DP 74LVC2G86GM 74LVC2G86GT JESD22-A114E MO-187 marking V86
    Text: 74LVC2G86 Dual 2-input EXCLUSIVE-OR gate Rev. 07 — 13 June 2008 Product data sheet 1. General description The 74LVC2G86 provides a dual 2-input EXCLUSIVE-OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these


    Original     		PDF 74LVC2G86 74LVC2G86 v86 5-pin 74LVC2G86DC 74LVC2G86DP 74LVC2G86GM 74LVC2G86GT JESD22-A114E MO-187 marking V86

    74LVC2G00

    Abstract: 74LVC2G00DC 74LVC2G00DP 74LVC2G00GD 74LVC2G00GM 74LVC2G00GT JESD22-A114E MO-187
    Text: 74LVC2G00 Dual 2-input NAND gate Rev. 07 — 10 June 2008 Product data sheet 1. General description The 74LVC2G00 provides a 2-input NAND gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.


    Original     		PDF 74LVC2G00 74LVC2G00 74LVC2G00DC 74LVC2G00DP 74LVC2G00GD 74LVC2G00GM 74LVC2G00GT JESD22-A114E MO-187

    74LVC2G08

    Abstract: 74LVC2G08DC 74LVC2G08DP 74LVC2G08GD 74LVC2G08GM 74LVC2G08GT JESD22-A114E MO-187 sot996
    Text: 74LVC2G08 Dual 2-input AND gate Rev. 08 — 9 June 2008 Product data sheet 1. General description The 74LVC2G08 provides a 2-input AND gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the 74LVC2G08 as a translator in a mixed 3.3 V and 5 V environment.


    Original     		PDF 74LVC2G08 74LVC2G08 74LVC2G08DC 74LVC2G08DP 74LVC2G08GD 74LVC2G08GM 74LVC2G08GT JESD22-A114E MO-187 sot996