MT4C4007JDJ-6
Abstract: MT4C4007JDJ-6L A4 marking EDO DRAM
Text: OBSOLETE 1 MEG x 4 EDO DRAM MT4C4007J DRAM FEATURES PIN ASSIGNMENT Top View Single +5V ±10% power supply JEDEC-standard pinout and packages High-performance CMOS silicon-gate process All inputs, outputs and clocks are TTL-compatible Refresh modes: RAS#-ONLY, CAS#-BEFORE- RAS#
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PDF
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MT4C4007J
024-cycle
128ms
20/26-Pin
MT4C4007JDJ-6
MT4C4007JDJ-6L
A4 marking
EDO DRAM
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MT4C4007JDJ-6
Abstract: MT4C4007J MT4C4007JDJ-6L
Text: MT4C4007J L 1 MEG x 4 DRAM TECHNOLOGY, INC. 1 MEG x 4 DRAM DRAM 5V, EDO PAGE MODE, OPTIONAL EXTENDED REFRESH FEATURES Single +5V ±10% power supply JEDEC-standard pinout and packages High-performance CMOS silicon-gate process All inputs, outputs and clocks are TTL-compatible
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Original
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PDF
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MT4C4007J
024-cycle
128ms
20/26-Pin
128ms
MT4C4007JDJ-6
MT4C4007JDJ-6L
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IBM025161LG5D60
Abstract: gm72v16821 MD908 KM48S2020 TC59R1809 GM72V1682 KM4232W259Q60 KM416S1120A IBM025171LG5D-70 KM44S4020AT
Text: Fujitsu Microelectronics Inc. Hitachi America Ltd. Hyundai Electronics America Inc. IBM Microelectronics LG Semicon America Inc. formerly Goldstar Mitsubishi Electronics America Inc. NEC Electronics Inc. Micron Technology Inc. Mosel Vitelic Inc. MoSys Inc.
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MB81141621
MB81141622
MB81G8322
MB81116421
TC59R1608
2ns500MHz
TC59R0808
IBM025161LG5D60
gm72v16821
MD908
KM48S2020
TC59R1809
GM72V1682
KM4232W259Q60
KM416S1120A
IBM025171LG5D-70
KM44S4020AT
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MT16D232M
Abstract: MT16D232 MT4C4007JDJ
Text: OBSOLETE 1, 2 MEG x 32 DRAM SIMMs MT8D132 X MT16D232(X) DRAM MODULE FEATURES PIN ASSIGNMENT (Front View) • JEDEC- and industry-standard pinout in a 72-pin, single in-line memory module (SIMM) • 4MB (1 Meg x 32) and 8MB (2 Meg x 32) • High-performance CMOS silicon-gate process
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Original
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PDF
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MT8D132
MT16D232
72-pin,
024-cycle
MT16D232M
MT4C4007JDJ
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edo dram 60ns 72-pin simm
Abstract: MT16D232
Text: MT8D132 X , MT16D232(X) 1 MEG, 2 MEG x 32 DRAM MODULES TECHNOLOGY, INC. 1 MEG, 2 MEG x 32 DRAM MODULE 4, 8 MEGABYTE, 5V, FAST PAGE OR EDO PAGE MODE FEATURES PIN ASSIGNMENT (Front View) • JEDEC- and industry-standard pinout in a 72-pin, single-in-line memory module (SIMM)
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Original
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PDF
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MT8D132
MT16D232
72-pin,
824mW
024-cycle
72-PiP
edo dram 60ns 72-pin simm
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MT41LC256K32D4
Abstract: BEDO RAM MT4C16270 Matsushita fp-m MT4LC4M4G6 MT4C1004J MT4C16257 MT4C4001J MT4LC1M16C3 MT4LC1M16E5
Text: TM Burst EDO DRAMs TECHNOLOGY, INC. 1 What are Burst EDO DRAMs? Burst EDO BEDO DRAMs are the Best Solution for 66 MHz Systems ❏ Standard DRAMs with shorter page mode cycle times ❏ EDO DRAMs that contain a pipeline stage and a 2-bit burst counter ❏
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EDO DRAM
Abstract: No abstract text available
Text: 1 MEG x 4 EDO DRAM M IC R O N I TFCHNOl.GOY l';C DRAM MT4C4007J FEATURES PIN ASSIGNMENT Top View Single +5V ±10% pow er supply JEDEC-standard pinout and packages High-performance CMOS silicon-gate process All inputs, outputs and clocks are TTL-compatible
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OCR Scan
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PDF
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MT4C4007J
024-cycle
128ms
20/26-Pin
EDO DRAM
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4c4007
Abstract: 4007J
Text: MT4C4007J L 1 MEG X 4 DRAM |u iic n o N 1 MEG x 4 DRAM DRAM 5V, EDO PAGE MODE, OPTIONAL EXTENDED REFRESH FEATURES PIN ASSIGNMENT (Top View) • • • • • S in g le + 5 V ± 1 0 % p o w er su p p ly JE D E C -sta n d a rd p in o u t and p ack ag es H ig h -p erfo rm a n ce C M O S silico n -g ate process
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OCR Scan
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PDF
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MT4C4007J
024-cy
20/26-Pin
T2/95
4c4007
4007J
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LIS-1024
Abstract: No abstract text available
Text: OBSOLETE M I C R O N 1 ^cnllvZ DRAM E G x 4 MT4C4007J FEATURES PIN ASSIGNMENT Top View • • • • • Single +5V +10% pow er supply JED EC-standard pinout and packages H igh-perform ance CM OS silicon-gate process All inputs, outputs and clocks are TTL-com patible
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OCR Scan
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PDF
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024-cycle
128ms
MT4C4007J
20/26-Pin
128ms
LIS-1024
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T4C4007JDJ-7
Abstract: No abstract text available
Text: PRELIMINARY MT4C4007J S 1 MEG X 4 DRAM M IC R O N 1 MEG x 4 DRAM DRAM 5V, EDO PAGE MODE, OPTIONAL SELF REFRESH FEATURES PIN ASSIGNMENT (Top View) • • • • • Single +5V ±10% power supply JEDEC-standard pinout and packages High-perform ance CM OS silicon-gate process
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OCR Scan
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PDF
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MT4C4007J
024-cycle
128ms
25-35ns
20/26-Pin
T4C4007JDJ-7
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Untitled
Abstract: No abstract text available
Text: MT4C4007J L 1 MEG X 4 DRAM (M IC R O N 1 MEG x 4 DRAM DRAM 5V, EDO PAGE MODE, OPTIONAL EXTENDED REFRESH PIN ASSIGNMENT (Top View) • • • • • Single +5V ±10% power supply JEDEC-standard pinout and packages High-performance CMOS silicon-gate process
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OCR Scan
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PDF
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MT4C4007J
024-cycle
128ms
20/26-Pin
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY .ü ïïi04,0^ !? -j, MEG x 4 DRAM « ch«oL„ „ « DRAM 1 MEG x 4 DRAM FEATURES * * » * «• Single +5V ±10% power supply JEDEC-standard pinout and packages High-perform ance CMOS silicon-gate process All inputs, outputs and clocks are TTL-com patible
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OCR Scan
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PDF
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024-cycle
128ms
25-35ns
128ms
MT4C4007J
001E024
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Untitled
Abstract: No abstract text available
Text: MT8D132 X , MT16D232(X) 1 MEG, 2 MEG x 32 DRAM MODULES MICRON I TÉCHNOICSY INC. DRAM 1 MEG, 2 MEG x 32 II E IV IV J U U L C 4. 8 MEGABYTE, SV, FAST PAGE OR EDO PAGE MODE FEATURES PIN ASSIGNMENT (Front View) • JEDEC- and industry-standard pinout in a 72-pin,
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OCR Scan
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PDF
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MT8D132
MT16D232
72-pin,
824mW
024-cycle
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T4C4007J
Abstract: No abstract text available
Text: OBSOLETE 1, 2 MEG X 32 DRAM SIMMs MICRON I TECHNOLOGY, INC. MT8D132 X MT16D232(X) DRAM MODULE FEATURES PIN ASSIGNMENT (Front View) • JED EC - and industry-standard pinout in a 72-pin, single in-line m em ory m odule (SIMM) • 4M B (1 M eg x 32) and 8MB (2 M eg x 32)
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OCR Scan
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PDF
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MT8D132
MT16D232
72-pin,
024-cycle
72-Pin
T4C4007J
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MT4C4007JDJ
Abstract: L32x MT4C4007 MT80132 MT160232 micron simm
Text: M ir -a r ìM I MT8D132 X , MT16D232(X) 1 MEG, 2 MEG X 32 DRAM MODULES DRAM 1 MEG, 2 MEG x 32 M O D U L E 4, 8 8 MEGABYTE, MEGABYTE, 5V, 5V, FAST R 4, PAGE OR EDO PAGE MODE FEATURES PIN ASSIGNMENT (Front View) • JEDEC- and industry-standard pinout in a 72-pin,
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OCR Scan
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PDF
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MT8D132
MT16D232
72-pin,
024-cycle
72MEG
MT80132
MTie0232
MT4C4007JDJ
L32x
MT4C4007
MT160232
micron simm
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MT4C4007JDJ-7
Abstract: MT4C4007JDJ7 marking 3GY MRP21
Text: PRELIMINARY iimiy—a n i v f wlt4C40Q7J S t MEG x: 4 DRAM 1 MEG x 4 DRAM DRAM 5V, EDO PAGE MODE, OPTIONAL SELF REFRESH ] MATURES • Single +5V ±10% pow er supply ■ JED EC-standard pinout and packages ■ High-performance C M O S silicon-gate process
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OCR Scan
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PDF
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wlt4C40Q7J
024-cycle
128ms
25-35ns
20/26-Pin
MT4C4007J
C1995.
MT4C4007JDJ-7
MT4C4007JDJ7
marking 3GY
MRP21
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EDO DRAM
Abstract: MT4C4007JDJ-6L MT4C4007JDJ-6
Text: 1 MEG x 4 EDO DRAM V IIC Z R C H V S DRAM M T4C 4007J FEATURES PIN ASSIGNMENT (Top View Single+5V ±10% power supply JEDEC-standard pinout and packages High-performance CMOS silicon-gate process All inputs, outputs and clocks are TTL-compatible Refresh modes: RAS#-ONLY, CAS#-BEFORE- RAS#
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OCR Scan
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PDF
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4007J
024-cycle
128ms
20/26-Pin
128ms
EDO DRAM
MT4C4007JDJ-6L
MT4C4007JDJ-6
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MT4C4007JDJ
Abstract: No abstract text available
Text: ADVANCE M T 9 D 1 3 6 A X, M T 1 8 D 2 3 6 A X 1 MEG, 2 MEG x 36 DR AM M O D U L E S DRAM MODULE 1 MEG, 2 MEG x 36 4, 8 MEGABYTE, 5V, ECC, EDO PAGE MODE FEATURES * * * * * * * * PIN ASSIGNMENT Front View Four CAS# ECC p in o u t in a 72-pin, single-in-line
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OCR Scan
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PDF
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72-Pin
72-pin,
024-cycle
MT4C4007JDJ
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