Untitled
Abstract: No abstract text available
Text: User's Guide SLOU307 – January 2011 DRV612EVM This user’s guide describes the operation of the DRV612 evaluation module. This document provides design information including a schematic, bill of materials, and printed circuit board PCB layout drawings.
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SLOU307
DRV612EVM
DRV612
DRV612EVM
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Untitled
Abstract: No abstract text available
Text: User's Guide SLOU288 – February 2010 DRV604PWPEVM DRV604PWPEVM This user's guide describes the operation of the evaluation module for the DRV604. The user’s guide also provides measurement data and design information like schematic, BOM and PCB layout.
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SLOU288
DRV604PWPEVM
DRV604.
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Untitled
Abstract: No abstract text available
Text: SN74SSTU32864D 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES623A – FEBRUARY 2005 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
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SN74SSTU32864D
25-BIT
SCES623A
14-Bit
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A115-A
Abstract: C101 SN74SSTU32864C SN74SSTU32864CGKER
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
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SN74SSTU32864C
25-BIT
SCES542B
14-Bit
A115-A
C101
SN74SSTU32864C
SN74SSTU32864CGKER
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A115-A
Abstract: C101 SN74SSTU32864C SN74SSTU32864CGKER
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
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SN74SSTU32864C
25-BIT
SCES542B
14-Bit
A115-A
C101
SN74SSTU32864C
SN74SSTU32864CGKER
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A115-A
Abstract: C101 SN74SSTU32864D SN74SSTU32864DGKER SSTL-18
Text: SN74SSTU32864D 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES623A – FEBRUARY 2005 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
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SN74SSTU32864D
25-BIT
SCES623A
14-Bit
A115-A
C101
SN74SSTU32864D
SN74SSTU32864DGKER
SSTL-18
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Untitled
Abstract: No abstract text available
Text: 74SSTUB32865 www.ti.com SLAS537 – NOVEMBER 2007 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 RDIMM PCB Layout • 1-to-2 Outputs Supports Stacked DDR2
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74SSTUB32865
SLAS537
28-BIT
56-BIT
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74SSTUB32865
Abstract: 74SSTUB32865ZJBR Q19A
Text: 74SSTUB32865 www.ti.com SLAS537 – NOVEMBER 2007 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 RDIMM PCB Layout • 1-to-2 Outputs Supports Stacked DDR2
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74SSTUB32865
SLAS537
28-BIT
56-BIT
74SSTUB32865
74SSTUB32865ZJBR
Q19A
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Untitled
Abstract: No abstract text available
Text: 74SSTUB32865A www.ti.com SLAS562 – NOVEMBER 2007 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 RDIMM PCB Layout • 1-to-2 Outputs Supports Stacked DDR2
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74SSTUB32865A
SLAS562
28-BIT
56-BIT
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74SSTUB32865A
Abstract: 74SSTUB32865AZJBR Q19A
Text: 74SSTUB32865A www.ti.com SLAS562 – NOVEMBER 2007 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 RDIMM PCB Layout • 1-to-2 Outputs Supports Stacked DDR2
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74SSTUB32865A
SLAS562
28-BIT
56-BIT
74SSTUB32865A
74SSTUB32865AZJBR
Q19A
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Untitled
Abstract: No abstract text available
Text: 74SSTUB32865A www.ti.com SLAS562 – NOVEMBER 2007 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 RDIMM PCB Layout • 1-to-2 Outputs Supports Stacked DDR2
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74SSTUB32865A
SLAS562
28-BIT
56-BIT
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Untitled
Abstract: No abstract text available
Text: 74SSTUB32865 www.ti.com SLAS537 – NOVEMBER 2007 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 RDIMM PCB Layout • 1-to-2 Outputs Supports Stacked DDR2
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74SSTUB32865
SLAS537
28-BIT
56-BIT
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54ACT16623
Abstract: 74ACT16623 74ACT16623DL 74ACT16623DLG4 74ACT16623DLR 74ACT16623DLRG4 75ACT16623
Text: 54ACT16623, 74ACT16623 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS152A – JANUARY 1991 – REVISED APRIL 1996 D D D D D D Members of the Texas Instruments Widebus Family Inputs are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout
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54ACT16623,
74ACT16623
16-BIT
SCAS152A
300-mil
25-mil
380-mil
ACT16623
54ACT16623
74ACT16623
74ACT16623DL
74ACT16623DLG4
74ACT16623DLR
74ACT16623DLRG4
75ACT16623
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Q11A
Abstract: Q13A SN74SSTUB32864 SN74SSTUB32864ZKER sb864
Text: SN74SSTUB32864 www.ti.com SCAS791A – OCTOBER 2006 – REVISED SEPTEMBER 2007 25-BIT CONFIGURABLE REGISTERED BUFFER FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 DIMM PCB Layout • Configurable as 25-Bit 1:1 or 14-Bit 1:2
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SN74SSTUB32864
SCAS791A
25-BIT
14-Bit
Q11A
Q13A
SN74SSTUB32864
SN74SSTUB32864ZKER
sb864
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Untitled
Abstract: No abstract text available
Text: 74SSTUB32864A www.ti.com SCAS838 – OCTOBER 2006 25-BIT CONFIGURABLE REGISTERED BUFFER • FEATURES • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer
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74SSTUB32864A
SCAS838
25-BIT
14-Bit
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Untitled
Abstract: No abstract text available
Text: 74SSTUB32864A www.ti.com SCAS838 – OCTOBER 2006 25-BIT CONFIGURABLE REGISTERED BUFFER • FEATURES • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer
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74SSTUB32864A
SCAS838
25-BIT
14-Bit
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74SSTUB32864AZKER
Abstract: Q11A Q13A
Text: 74SSTUB32864A www.ti.com SCAS838 – OCTOBER 2006 25-BIT CONFIGURABLE REGISTERED BUFFER • FEATURES • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer
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74SSTUB32864A
SCAS838
25-BIT
14-Bit
74SSTUB32864AZKER
Q11A
Q13A
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Untitled
Abstract: No abstract text available
Text: 74SSTUB32864A www.ti.com SCAS838 – OCTOBER 2006 25-BIT CONFIGURABLE REGISTERED BUFFER • FEATURES • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer
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74SSTUB32864A
SCAS838
25-BIT
14-Bit
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Untitled
Abstract: No abstract text available
Text: 74SSTUB32864A www.ti.com SCAS838 – OCTOBER 2006 25-BIT CONFIGURABLE REGISTERED BUFFER • FEATURES • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer
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74SSTUB32864A
SCAS838
25-BIT
14-Bit
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Untitled
Abstract: No abstract text available
Text: SN74SSTUB32864 www.ti.com SCAS791A – OCTOBER 2006 – REVISED SEPTEMBER 2007 25-BIT CONFIGURABLE REGISTERED BUFFER FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 DIMM PCB Layout • Configurable as 25-Bit 1:1 or 14-Bit 1:2
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SN74SSTUB32864
SCAS791A
25-BIT
14-Bit
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54AC16620
Abstract: 74AC16620 74AC16620DL 74AC16620DLR
Text: 54AC16620, 74AC16620 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS239A – JULY 1990 – REVISED APRIL 1996 D D D D D D D Members of the Texas Instruments Widebus Family 3-State Outputs Drive Bus Lines Directly Flow-Through Architecture Optimizes PCB Layout
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54AC16620,
74AC16620
16-BIT
SCAS239A
500-mA
300-mil
25-mil
380-mil
AC16620
54AC16620
74AC16620
74AC16620DL
74AC16620DLR
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Untitled
Abstract: No abstract text available
Text: 54AC16620, 74AC16620 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS239A – JULY 1990 – REVISED APRIL 1996 D D D D D D D Members of the Texas Instruments Widebus Family 3-State Outputs Drive Bus Lines Directly Flow-Through Architecture Optimizes PCB Layout
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54AC16620,
74AC16620
16-BIT
SCAS239A
500-mA
300-mil
25-mil
380-mil
AC16620
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Untitled
Abstract: No abstract text available
Text: 74SSTUB32868 www.ti.com SCAS835B – JUNE 2007 – REVISED NOVEMBER 2007 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 DIMM PCB Layout • 1-to-2 Outputs Supports Stacked DDR2 DIMMs
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74SSTUB32868
SCAS835B
28-BIT
56-BIT
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A115-A
Abstract: C101 SN74SSTU32866A SN74SSTU32866AZKER
Text: SN74SSTU32866A 25ĆBIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESSĆPARITY TEST SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007 D Member of the Texas Instruments D D D D D D D D Checks Parity on DIMM-Independent Data Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
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SN74SSTU32866A
25BIT
SCAS803A
25-Bit
14-Bit
A115-A
C101
SN74SSTU32866A
SN74SSTU32866AZKER
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