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    PO74G112A

    Abstract: T flip flop pin configuration JK flip flop IC diagram
    Text: PO74G112A www.potatosemi.com DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP FLOP WITH CLEAR AND PRESET 74 Series Noise Cancellation GHz Logic FEATURES: DESCRIPTION: . Patented technology . Specified From –40°C to 85°C, –40°C to 125°C, and –55°C to 125°C


    Original     		PDF PO74G112A 750MHz 5000-VHuman-BodyModel A114-A) 200-VMachineModel A115-A) 16pin 150mil 173mil PO74G112A T flip flop pin configuration JK flip flop IC diagram