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Catalog Datasheet	MFG & Type	PDF	Document Tags
CDC318 Abstract: No abstract text available Text: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps	Original	PDF	CDC318 18-LINE SCAS587B 1-to-18 MIL-STD-883, 48-Pin CDC318
Untitled Abstract: No abstract text available Text: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps	Original	PDF	CDC318 18-LINE SCAS587B 1-to-18 MIL-STD-883, 48-Pin
CDC318 Abstract: CDC318DL CDC318DLR Text: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps	Original	PDF	CDC318 18-LINE SCAS587B 1-to-18 MIL-STD-883, 48-Pin CDC318 CDC318DL CDC318DLR
CDC318 Abstract: No abstract text available Text: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps	Original	PDF	CDC318 18-LINE SCAS587B 1-to-18 MIL-STD-883, 48-Pin CDC318
Untitled Abstract: No abstract text available Text: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps	Original	PDF	CDC318 18-LINE SCAS587B 1-to-18 MIL-STD-883, 48-Pin
TL 650 ht Abstract: No abstract text available Text: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH \|2C CONTROL INTERFACE SCAS587B - JANUARY 1997 - REVISED MARCH 1998 High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM SDRAM Clock Buffering Applications Output Skew, tSk(0), Less Than 250 ps Pulse Skew, tSk(P), Less Than 650 ps	OCR Scan	PDF	CDC318 18-LINE SCAS587B 1-to-18 MIL-STD-883, 48-Pin TL 650 ht