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    ST18930 Search Results

    ST18930 Datasheets (2)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    ST18930CFN STMicroelectronics Digital Signal Processor Scan PDF
    ST18930CP STMicroelectronics Digital Signal Processor Scan PDF

    ST18930 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    68951

    Abstract: TS68951 BAT43 equivalent RC6 philips DIP28 PLCC28 TS68950 TS68951CFN TS68951CP TS68952
    Text: TS68951 MODEM RECEIVE ANALOG INTERFACE . . . . . . . TWO CHANNEL 12-BIT ANALOG TO DIGITAL CONVERTER FOR RECEPTION OF DIGITAL DATA FROM THE TELEPHONE LINE AND ECHO CANCELLATION WITH ASYNCHRONOUS MULTIPLEXING OF 2 PLESIOCHRONOUS CHANNELS PROGRAMMABLE SWITCHED CAPACITOR


    Original     		PDF TS68951 12-BIT DIP28 PLCC28 PMPLCC28 68951 TS68951 BAT43 equivalent RC6 philips DIP28 TS68950 TS68951CFN TS68951CP TS68952

    fsk arm dtmf

    Abstract: SCR c106 PIN CONFIGURATION active tone control circuit with TL072 scr C106 DIP28 DIP48 PLCC28 PLCC52 c19f TS7538
    Text: TS75C96 V.32, V.29, V.27ter, V.22bis, V.22, V.23, BELL 212A, BELL 103 MODEM CHIP SET . . . . . . . . . . . . . . . . . ADVANCE DATA CCITT V.32, V.22bis, V.22, V.21, V.23, Bell 212A, Bell 103 COMPATIBLE MODEM CHIP SET CCITT V.29, V.27ter FOR FAX APPLICATIONS


    Original     		PDF TS75C96 27ter, 22bis, 27ter 300bps 22bis 29/4800bps fsk arm dtmf SCR c106 PIN CONFIGURATION active tone control circuit with TL072 scr C106 DIP28 DIP48 PLCC28 PLCC52 c19f TS7538

    TS7538

    Abstract: SDS S4 24V TS7532 0-600C SDS S4 - 24V
    Text: TS75C96 V.32, V.29, V.27ter, V.22bis, V.22, V.23, BELL 212A, BELL 103 MODEM CHIP SET . . . . . . . . . . . . . . . . . ADVANCE DATA CCITT V.32, V.22bis, V.22, V.21, V.23, Bell 212A, Bell 103 COMPATIBLE MODEM CHIP SET CCITT V.29, V.27ter FOR FAX APPLICATIONS


    Original     		PDF TS75C96 27ter, 22bis, 27ter 300bps 22bis 29/4800bps PMPLCC52 TS7538 SDS S4 24V TS7532 0-600C SDS S4 - 24V

    Untitled

    Abstract: No abstract text available
    Text: TS68950 MODEM TRANSMIT ANALOG INTERFACE TWO CHANNEL DIGITAL TO ANALOG CONVERTER FOR TRANSMISSION OF DIGITAL DATA TO THE TELEPHONE LINE AND ECHO CANCELLATION 6TH ORDER SWITCHED CAPACITOR LOW PASS FILTER FOR ADAPTATION TO THE TELEPHONE BANDWIDTH OUTPUT CONTINUOUS TIME SMOOTHING


    Original     		PDF TS68950 TS68950 TS68951

    DIP28

    Abstract: PLCC28 TS68950 TS68951 TS68952 TS68952CFN TS68952CP programming controle system with c rc711
    Text: TS68952 MODEM TRANSMIT/RECEIVE CLOCK GENERATOR . . . . . . INDEPENDANT TRANSMIT AND RECEIVE CLOCK GENERATORS WITH DIGITAL PHASE LOCKED LOOPS TRANSMIT DPLL SYNCHRONIZATION ON EXTERNAL TERMINAL CLOCK OR INTERNAL RECEIVE CLOCK RECEIVE DPLL SYNCHRONIZATION CONTROLLED FROM THE BUS


    Original     		PDF TS68952 TS68952 TS68950 PLCC28 PMPLCC28 DIP28 TS68951 TS68952CFN TS68952CP programming controle system with c rc711

    2900Hz

    Abstract: Polarised capacitor rr1 440
    Text: TS68951 MODEM RECEIVE ANALOG INTERFACE . . . . . . . TWO CHANNEL 12-BIT ANALOG TO DIGITAL CONVERTER FOR RECEPTION OF DIGITAL DATA FROM THE TELEPHONE LINE AND ECHO CANCELLATION WITH ASYNCHRONOUS MULTIPLEXING OF 2 PLESIOCHRONOUS CHANNELS PROGRAMMABLE SWITCHED CAPACITOR


    Original     		PDF TS68951 12-BIT DIP28 TS68951 2900Hz Polarised capacitor rr1 440

    V27bis

    Abstract: 68950 PLCC28 TS68950 TS68950CFN TS68950CP TS68951 TS68952 V26BIS modem circuit echo
    Text: TS68950 MODEM TRANSMIT ANALOG INTERFACE TWO CHANNEL DIGITAL TO ANALOG CONVERTER FOR TRANSMISSION OF DIGITAL DATA TO THE TELEPHONE LINE AND ECHO CANCELLATION 6TH ORDER SWITCHED CAPACITOR LOW PASS FILTER FOR ADAPTATION TO THE TELEPHONE BANDWIDTH OUTPUT CONTINUOUS TIME SMOOTHING


    Original     		PDF TS68950 TS68950 PLCC28 PMPLCC28 V27bis 68950 TS68950CFN TS68950CP TS68951 TS68952 V26BIS modem circuit echo

    TDC 8117

    Abstract: TS68952CP
    Text: TS68952 MODEM TRANSMIT/RECEIVE CLOCK GENERATOR . . . . . . INDEPENDANT TRANSMIT AND RECEIVE CLOCK GENERATORS WITH DIGITAL PHASE LOCKED LOOPS TRANSMIT DPLL SYNCHRONIZATION ON EXTERNAL TERMINAL CLOCK OR INTERNAL RECEIVE CLOCK RECEIVE DPLL SYNCHRONIZATION CONTROLLED FROM THE BUS


    Original     		PDF TS68952 TS68952 TS68950 TDC 8117 TS68952CP

    SDS st2

    Abstract: 32QAM BLOCK DIAGRAM SGS-THOMSON modem DIP28 DIP48 PLCC28 PLCC52 TS75C32 TS75C320CP DTMF DEcoder i2c
    Text: TS75C32 V.32, V.22bis, V.22, V.23, V.21, BELL 212A, BELL 103 MODEM CHIP SET CCITT V.32, V22bis, V.22, V.21, V.23, Bell 212A, Bell 103 COMPATIBLE MODEM CHIP SET INTEGRATED IMPLEMENTATION ON THREE DSP AND THREE MAFE CHIPS FULL DUPLEX OPERATION FROM 9600 TO 300BPS


    Original     		PDF TS75C32 22bis, V22bis, 300BPS 22bis PLCC52 SDS st2 32QAM BLOCK DIAGRAM SGS-THOMSON modem DIP28 DIP48 PLCC28 TS75C32 TS75C320CP DTMF DEcoder i2c

    ncl 071

    Abstract: PGA121 4kx16 ram "saturation flag" INSTRUCTION SET motorola 6800 intel 68000 INSTRUCTION SET motorola 1031 PLCC52 24CCR 6800 intel microprocessor pin diagram
    Text: SGS-THOMSON ¿ 5 7 IL itg T T ^ O R O D Ê S ST18930/31 DIGITAL SIGNAL PROCESSOR 80 ns INSTRUCTION CYCLE TIME ‘ 1.2 |i CMOS technology PARALLEL HARVARD ARCHITECTURE SEPARATED PROGRAM AND DATA BUSES THREE DATA BUSES STRUCTURE DUAL EXTERNAL BUSES ONE CYCLE 16-BIT R/W OPERATION ON EX­


    OCR Scan     		PDF ST18930/31 16-BIT 32-BIT ST18930 ST18931 ncl 071 PGA121 4kx16 ram "saturation flag" INSTRUCTION SET motorola 6800 intel 68000 INSTRUCTION SET motorola 1031 PLCC52 24CCR 6800 intel microprocessor pin diagram

    Untitled

    Abstract: No abstract text available
    Text: r z 7 S C S -T H O M S O N « « L E M « ! _ T S 6 8 9 5 2 ^ 7# MODEM TRANSMIT/RECEIVE CLOCK GENERATOR • INDEPENDANT TRANSMIT AND RECEIVE CLOCK GENERATORS WITH DIGITAL PHASE LOCKED LOOPS ■ TRANSMIT DPLL SYNCHRONIZATION ON EXTERNAL TERMINAL CLOCK OR INTERNAL


    OCR Scan     		PDF TS68952 50-pins TS68930 TS68950/51/52

    Untitled

    Abstract: No abstract text available
    Text: ¿= 7 * > S G S -T H O M S O N J i. B ü il[ l g I [ L im ( M D ( g § T S 6 8 9 5 0 MODEM TRANSMIT ANALOG INTERFACE • TWO CHANNEL DIGITAL TO ANALOG CON­ VERTER FOR TRANSMISSION OF DIGITAL DATA TO THE TELEPHONE LINE AND ECHO CANCELLATION ■ 6TH ORDER SWITCHED CAPACITOR LOW


    OCR Scan     		PDF TheTS68950 7H2H237 PLCC28

    ST188

    Abstract: No abstract text available
    Text: r z 7 Ä T# S C S -T H O M S O N & y i O T T M « S T 1 8 9 4 0 /4 1 DIGITAL SIGNAL PROCESSOR MAIN FEATURES • 100ns MACHINE CYCLE TIME 1.2 CMOS Technology ■ PARALLEL HARVARD ARCHITECTURE ■ TRIPLE DATA BUSES STRUCTURE ■ 3 DATA MODES . SINGLE PRECISION


    OCR Scan     		PDF 100ns 32-BIT ST188

    YA128

    Abstract: HDS-220 RCA 1A15 procesor P6E1 4x32 lcd BU 3150 MBS 6 B6 ST18 ST18941
    Text: SGS-THOMSON ST18940/41 DIGITAL SIGNAL PROCESSOR MAIN FEATURES • 100ns MACHINE CYCLE TIME 1.2 CMOS Technology . PARALLEL HARVARD ARCHITECTURE ■ TRIPLE DATA BUSES STRUCTURE . 3 DATA MODES . SINGLE PRECISION . DOUBLE PRECISION . COMPLEX ■ 32-BIT INSTRUCTION


    OCR Scan     		PDF ST18940/41 100ns 32-BIT 16-BIT YA128 HDS-220 RCA 1A15 procesor P6E1 4x32 lcd BU 3150 MBS 6 B6 ST18 ST18941

    EPR48

    Abstract: LCD 2 x 16 ia87
    Text: r = 7 Ä T # S G S - T H O M S O N R Æ Œ (ô m i(O T (ô K S S T 1 8 9 3 0 /3 1 DIGITAL SIGNAL PR O C ESSO R • 80 ns INSTRUCTION CYCLE TIME ‘ (1.2 (i CMOS technology) ■ PARALLEL HARVARD ARCHITECTURE ■ SEPARATED PROGRAM AND DATA BUSES ■ THREE DATA BUSES STRUCTURE


    OCR Scan     		PDF 16-BIT 32-BIT ST18930 ST18931 64Kx32-bit EPR48 LCD 2 x 16 ia87

    DSP/teaklite 3 instruction opcode

    Abstract: No abstract text available
    Text: r i j S G S -T H O M S O N *7 M TS75C32 V.32, V.22bis, V.22, V.23, V.21, BELL 212A, BELL 103 MODEM CHIP SET ADVANCE DATA • CCITT V.32, V22bis, V.22, V.21, V.23, Bell 212A, Bell 103 COMPATIBLE MODEM CHIPSET ■ INTEGRATED IMPLEMENTATION ON THREE DSP AND THREE MAFE CHIPS


    OCR Scan     		PDF TS75C32 22bis, V22bis, 300BPS 22bis DSP/teaklite 3 instruction opcode

    Untitled

    Abstract: No abstract text available
    Text: ¿ = 7 S C S -T H O M S O N *JÆ, 6aiD g ®IlL[I irMDȧ TS68951 MODEM RECEIVE ANALOG INTERFACE • TWO CHANNEL 12-BIT ANALOG TO DIGITAL CONVERTER FOR RECEPTION OF DIGITAL DATA FROM THE TELEPHONE LINE AND ECHO CANCELLATION (WITH ASYNCHRO­ NOUS MULTIPLEXING OF 2 PLESIOCHRONOUS CHANNELS


    OCR Scan     		PDF TS68951 12-BIT DIP28 TS68951 7b307 PLCC28

    Untitled

    Abstract: No abstract text available
    Text: / T T SG S-THOM SO N *7 .t. ö!!i!D»i[LII gTl(MD(g§ TS75C32 V . 3 2 , V . 2 2 b is , V . 2 2 , V . 2 3 , V . 2 1 , B E LL 21 2A , B E LL 103 M O D E M C H IP S E T ADVANCE DATA • CCITT V.32, V22bis, V.22, V.21, V.23, Bell 212A, Bell 103 COMPATIBLE MODEM


    OCR Scan     		PDF TS75C32 V22bis, 300BPS 22bis 0D7b424

    Untitled

    Abstract: No abstract text available
    Text: S. ? 1993 /= T #. ^7 S C S -T H O M S O N HKSW M S 5 TS 7538 ASYNCHRONOUS-SYNCHRONOUS AND SERIAL-PARALLEL CONVERTER • . . ■ ■ ■ ■ . ■ ■ ■ BOTH ASYNCH R O N O U S AND SYNCHRO­ NOUS M O DES OF OPERATION INCLUDING FULL CCITT V.14 ARHYTHM IC CHARAC­


    OCR Scan     		PDF

    Untitled

    Abstract: No abstract text available
    Text: 0011103 1 ‘" P 7 5 ^ 2 -O S S G S -T H O M S O N * TS75C25 t 7 V.22 BIS, V.22, BELL 212, V.21 V.23, BELL 103 M O D EM C H IP SET ADVANCE DATA • CCITT V.22 BIS COMPATIBLE MODEM CHIP of modems complying with CCITT V.21, V.22, V.23, SET and BELL 103, 212 recommendations. The modem


    OCR Scan     		PDF TS75C25 TS7542) ST18930 TS75C250) TS75C250.

    Untitled

    Abstract: No abstract text available
    Text: I S G S -T H O M S O N ¿ 5 7 TS68951 me MODEM RECEIVE ANALOG INTERFACE TWO CHANNEL 12-BIT ANALOG TO DIGITAL CONVERTER FOR RECEPTION OF DIGITAL DATA FROM THE TELEPHONE LINE AND ECHO CANCELLATION with asynchronous multiplexing of 2 plesiochronous channels


    OCR Scan     		PDF TS68951 12-BIT TS68951 50-pins TS68930 TS68950/51/52

    3AD3

    Abstract: barrel shifter block diagram intel 68000 INSTRUCTION SET lb 8930 TS68930 TS68931 block diagram for barrel shifter aos Manufacturing date code "saturation flag" xacu
    Text: f Z 7 SGS-THOMSON m 7# [RÆQ g[i? iUi Tr^©[ïaO(gS TS68930/31 DIGITAL SIGNAL PR O C ESSO R 160ns INSTRUCTION CYCLE TIME PARALLEL HARVARD ARCHITECTURE SEPARATED PROGRAM AND DATA BUSES THREE DATA BUSES STRUCTURE DUAL EXTERNAL BUSES ONE CYCLE 16-BIT R M OPERATION ON EX­


    OCR Scan     		PDF TS68930/31 160ns 16-BIT 32-BIT 512x16-BIT TS68930 3AD3 barrel shifter block diagram intel 68000 INSTRUCTION SET lb 8930 TS68931 block diagram for barrel shifter aos Manufacturing date code "saturation flag" xacu

    D347D

    Abstract: ST18940 "saturation flag" 32 bit barrel shifter circuit diagram using multi
    Text: f Z 7 SGS-THOMSON Ä 7 # O^D l^@llLli@¥l^@ß!lfl©i TS68930/31 DIGITAL SIGNAL PROCESSOR • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 160ns INSTRUCTION CYCLE TIME PARALLEL HARVARD ARCHITECTURE SEPARATED PROGRAM AND DATA BUSES THREE DATA BUSES STRUCTURE


    OCR Scan     		PDF TS68930/31 160ns 16-BIT 32-BIT TS68930 TS68931 D347D ST18940 "saturation flag" 32 bit barrel shifter circuit diagram using multi

    tsl usc1

    Abstract: HD7x BL342
    Text: S G S -T H O M S O N TS75C96 V.32, V.29, V.27ter, V.22bis, V.22, V.23, BELL 212A, BELL 103 MODEM CHIP SET ADVANCE DATA CCITT V.32, V.22bis, V.22, V.21, V.23, Bell 212A, Bell 103 COMPATIBLE MODEM CHIP SET CCITT V.29, V.27ter FOR FAX APPLICA­ TIONS INTEGRATED IMPLEMENTATION ON THREE


    OCR Scan     		PDF TS75C96 27ter, 22bis, 27ter 300bps 22bis 29/4800bps 0G7b471 tsl usc1 HD7x BL342