TRISTATE NAND GATE Search Results

TRISTATE NAND GATE Result Highlights (5)

Part	Manufacturer	Description
54LS126A/BCA	Rochester Electronics LLC	54LS126 - Quad bus buffer gates with Tristate Output - Dual marked (M38510/32302BCA)
TC4011BP	Toshiba Electronic Devices & Storage Corporation	CMOS Logic IC, 2-Input/NAND, DIP14
TC4093BP	Toshiba Electronic Devices & Storage Corporation	CMOS Logic IC, 2-Input/NAND, DIP14
7UL1G00NX	Toshiba Electronic Devices & Storage Corporation	One-Gate Logic(L-MOS), 2-Input/NAND, XSON6, -40 to 125 degC
DFE2016CKA-1R0M=P2	Murata Manufacturing Co Ltd	Fixed IND 1uH 1800mA NONAUTO

TRISTATE NAND GATE Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
tristate xnor gate Abstract: tristate xor gate Tri-State Buffer CMOS SLG74LB1G99 tristate xor SLG74LB1G99V 74LVC1G99 74LVC1G99DP SN74AUP1G99 SN74LVC1G99 Text: SLG74LB1G99 GreenLIBTM ULTRA-CONFIGURABLE MULTIPLE FUNCTION GATE WITH TRI-STATE OUTPUT General Description Features The GreenLIB provides a low voltage, ultra-configurable, • Pb-Free / RoHS Compliant multiple function gate with one Tri-State Output. The device	Original	SLG74LB1G99 000-0074LB1G99-11 tristate xnor gate tristate xor gate Tri-State Buffer CMOS SLG74LB1G99 tristate xor SLG74LB1G99V 74LVC1G99 74LVC1G99DP SN74AUP1G99 SN74LVC1G99	PDF
octal Bilateral Switches Abstract: MM74HC14M MM74HC138M CD4025BCM MM74HC00M MM74HC74AM MM74HC125M MM74HC04M cd4046bcm cd4052bcm Text: 1/3 CMOS LOGIC MM74HC SERIES MM74HCT/U SERIES • HIGH SPEED CMOS TECHNOLOGY, CMOS DRIVE LEVELS, SPEED COMPARABLE TO 74LS SERIES Part Number Description • HIGH SPEED CMOS TECHNOLOGY, TTL DRIVE LEVELS, SPEED COMPARABLE TO 74LS SERIES SQP £ ea. Gates & Inverters	Original	MM74HC MM74HC00M MM74HC02M MM74HC04M MM74HC08M MM74HC14M MM74HC32M MM74HC86M MM74HC132M MM74HC74AM octal Bilateral Switches MM74HC138M CD4025BCM MM74HC125M cd4046bcm cd4052bcm	PDF
TTL 1-of-8 encoder Abstract: 74LS 2-input OR gate 74LS series logic gates 3 input nand gate 74LS series logic gates 3 input or gate 74F374SC Text: 1/2 TTL LOGIC 74F SERIES 74F SERIES • 74F: EXCELLENT SPEED/POWER CONSUMPTION COMBINATION Part Number Description SQP £ ea. Gates & Inverters 74F00SC Quad 2-Input NAND Gate 74F02SC Quad 2-Input NOR Gate 74F04SC Hex Inverter 74F08SC Quad 2-Input AND Gate	Original	74F164ASC 74F194SC 74F299SC 74F350SC 74F378SC 74F379SC 74F398SC 74F399SC 74F675ASC 74F676SC TTL 1-of-8 encoder 74LS 2-input OR gate 74LS series logic gates 3 input nand gate 74LS series logic gates 3 input or gate 74F374SC	PDF
z63n Abstract: t28000 z65n 07in M6008 mitsubishi lable fr1s MITSUBISHI GATE ARRAY z66n R12W Text: A m itsu b ish i ELECTRO N IC DEVICE GROUP P R E LIM IN A R Y M6008X 0.8 Jim CMOS GATE ARRAYS Mitsubishi M6008X Series 0.8 Jim CMOS Gate Arrays INTRODUCTION Mitsubishi offers sub-m icron CMOS Gate Arrays us ing a 0.8 micron drawn twin well silicon gate process	OCR Scan	M6008X MDS-GA-02-03-91 z63n t28000 z65n 07in M6008 mitsubishi lable fr1s MITSUBISHI GATE ARRAY z66n R12W	PDF
atmel 216 Abstract: ECL IC NAND CQFP 256 PIN actel Atmel 642 PO22 tri state ATL35 atmel 334 20PCI atmel h 952 Text: Features • High-speed - 150 ps Gate Delay - 2-input NAND, FO = 2 nominal • Up to 2.7 Million Used Gates and 976 Pins • System Level Integration Technology – Cores: ARM7TDMI and AVR RISC Microcontrollers, OakDSP™ and LodeDSPCores™, 10T/100 Ethernet MAC, USB and PCI Cores	Original	10T/100 ATL35 0802E 10/99/0M atmel 216 ECL IC NAND CQFP 256 PIN actel Atmel 642 PO22 tri state atmel 334 20PCI atmel h 952	PDF
PO61 Abstract: ATMEL 340 atmel 424 ATLS60 ATL60 ttl buffer 3.6v Tri-State Buffer bga ambit inverter circuit AOI222 ATMEL 218 Text: Features • • • • • • • • 0.6 µm Drawn Gate Length 0.5 µm Leff Sea-of-Gates Architecture with Triple Level Metal 5.0V, 3.3V and 2.0V Operation including Mixed Voltages On-chip Phase Locked Loop Available to Synthesize Frequencies up to 150 MHz and	Original	ATL60 0388C 11/99/xM PO61 ATMEL 340 atmel 424 ATLS60 ttl buffer 3.6v Tri-State Buffer bga ambit inverter circuit AOI222 ATMEL 218	PDF
TEMIC PLD Abstract: PRU10 PRD8 buffer 8x Structure of D flip-flop DFFSR AOI222 AOI2223 AOI2223H AOI222H MH1099 Text: MH1 1.6 Million gates Sea of Gates / Embedded Arrays 1. Description The MH1 Series Gate Array and Embedded Array families from TEMIC are fabricated in a 0.35µ CMOS process, with up to 3 levels of metal. This family features arrays with up to 1.6 million routable gates and 600 pins. The	Original		PDF
transistor nd8 Abstract: BT4R ISB28000 bt8c pMOS NAND GATE MUX21L AN720 BUT12 BUT18 BUT24 Text: ISB28000 SERIES HCMOS EMBEDDED ARRAY PRELIMINARY DATA FEATURES Combines Standard Cell features with Sea Of Gates time to market. 0.7 micron triple layer metal HCMOS process featuring self-aligned twin tub N and P wells, low resistance polysilicide gates and thin metal oxide.	Original	ISB28000 transistor nd8 BT4R bt8c pMOS NAND GATE MUX21L AN720 BUT12 BUT18 BUT24	PDF
atmel 424 Abstract: AMBIT inverter atmel 545 ATMEL 340 crystal oscillator buffer Structure of D flip-flop DFFSR s051 crystal OAI222 CMOS Transmission gate Specifications Tri-State Buffer CMOS Text: Features • 0.5 µm Drawn Gate Length 0.45µm Leff Sea-of-Gates Architecture With Triple Level Metal • 3.3V Operation • 5.0V Compatible Input Buffers • On-chip Phase Locked Loop (PLL) Available to Synthesize Frequencies up to 150 MHz • • • •	Original	ATL50 0753B 11/99/xM atmel 424 AMBIT inverter atmel 545 ATMEL 340 crystal oscillator buffer Structure of D flip-flop DFFSR s051 crystal OAI222 CMOS Transmission gate Specifications Tri-State Buffer CMOS	PDF
CB12000 Abstract: cd 4847 bt8c dc to ac inverter schematic CB22000 ld3p FD11S FD3S BUT12 BUT18 Text: CB22000 SERIES HCMOS STANDARD CELL GENERAL DESCRIPTION FEATURES 0.7 micron, double layer metal HCMOS4T process featuring self-aligned twin tub N and P wells, low resistance polysilicide gates and thin metal oxide. 2 - input NAND ND2P delay of 0.30 ns (typ)	Original	CB22000 CB12000 cd 4847 bt8c dc to ac inverter schematic ld3p FD11S FD3S BUT12 BUT18	PDF
circuit diagram of Tri-State Buffer using CMOS Abstract: verilog code for UART with BIST capability block diagram for UART with BIST capability tri state AT28 vhdl code for flip-flop vhdl pid verilog code pid controller free vhdl code for usart Text: Features • 0.5 µm Drawn Gate Length 0.45 µm Leff Sea-of-Gates Architecture with • • • • • Triple-level Metal Embedded E2 Memory up to 256 Kb 3.3V Operation with 5.0V Tolerant Input and Output Buffers High-speed, 200 ps Gate Delay, 2-input NAND, FO = 2 Nominal	Original	10T/100 ATL50/E2 1173D 11/99/1M circuit diagram of Tri-State Buffer using CMOS verilog code for UART with BIST capability block diagram for UART with BIST capability tri state AT28 vhdl code for flip-flop vhdl pid verilog code pid controller free vhdl code for usart	PDF
Untitled Abstract: No abstract text available Text: M T C -1 2 0 0 0 C M O S 1 .2 u Standard Cell Library Services CMOS Family Features • Technology: - 1.2 micron tw in -w ell CMOS process w ith polycide gates, double layer m etal, linear Ihin oxide capacitors and high ohmic resistors - Shrink capability to	OCR Scan	BHDA08A BHAD12A BHSD14A	PDF
74AC367 Abstract: 74ACT705 74ac2526 74ac2525 54AC/74AC2525 Text: Section 4 Contents 54AC/74AC00 Quad 2-Input NAND G a te . 54ACT/74ACT00 Quad 2-Input NAND Gate .	OCR Scan	54AC/74AC00 54ACT/74ACT00 54AC/74AC02 54ACT/74ACT02 54AC/74AC04 54ACT/74ACT04 AC2525 54AC/74AC2526 54AC/74AC2708 54ACT/74ACT2708 74AC367 74ACT705 74ac2526 74ac2525 54AC/74AC2525	PDF
Untitled Abstract: No abstract text available Text: GEC PLESSEY DS3598-3.4 MA9000 Series SILICON-ON-SAPPHIRE RADIATION HARD GATE ARRAYS The logic building block for the GPS double level metal C M O S /S O S ga te arrays is a fo u r tra n s is to r ‘c e ll-u n it’ equivalent in size to a 2 input NAND gate. Back to back cellunits as illustrated, organised in rows, form the core of the	OCR Scan	DS3598-3 MA9000 D0242bl 3Sx24nnnxxxxx 37bflS22 00242b2	PDF

PO88 Abstract: ttl buffer AOI222 AOI2223 AOI2223H AOI222H MH1099 MH1242 PRD21 PRD29V5 Text: Features • High Speed - 170 ps Gate Delay - 2 input NAND, FO=2 nominal • Up to 1.6 Million Used Gates and 596 pads, with 3.3V, 3V, and 2.5V libraries • System Level Integration Technology Cores on request: SRAM and TRAM (Gate Level or Embedded) • I/O Interfaces:	Original	250MHz 220MHz 800MHz 5962-01B01 PO88 ttl buffer AOI222 AOI2223 AOI2223H AOI222H MH1099 MH1242 PRD21 PRD29V5	PDF
full adder circuit using nor gates Abstract: D-latch DIL40 DIL48 half adder ttl half adder circuit using nor and nand gates microprocessor radiation hard datasheet SRDL DIL14 DIL16 Text: MA9000 Series MAY 1995 DS3598-3.4 MA9000 Series SILICON-ON-SAPPHIRE RADIATION HARD GATE ARRAYS The logic building block for the GPS double level metal CMOS/SOS gate arrays is a four transistor ‘cell-unit’ equivalent in size to a 2 input NAND gate. Back to back cellunits as illustrated, organised in rows, form the core of the	Original	MA9000 DS3598-3 full adder circuit using nor gates D-latch DIL40 DIL48 half adder ttl half adder circuit using nor and nand gates microprocessor radiation hard datasheet SRDL DIL14 DIL16	PDF
m6845 Abstract: NA51 transistor AMI 52 732 V DL651 M82530 MXI21 dl541 DF421 DF101 grid tie inverter schematics Text: “The new 0.6µm gate array and standard cell families from AMI provide outstanding quality and selection . . . setting performance standards in 0.6µm ASIC products . . . ” • 130 ps gate delays fanout = 2, interconnect length = 0mm ■ Double and Triple Metal Interconnect; up to 900,000 gate	Original	Table128, m6845 NA51 transistor AMI 52 732 V DL651 M82530 MXI21 dl541 DF421 DF101 grid tie inverter schematics	PDF
Transistor Equivalent list po55 Abstract: Structure of D flip-flop DFFSR tristate buffer sis 968 PO-44Z PRU11 AC/DC drive nec 78054 PO22 tristate buffer cmos Text: Features • High Speed - 180 ps Gate Delay - 2 input NAND, FO=2 nominal • Up to 1.198 M Used Gates and 512 Pads with 3.3 V, 3V and 2.5V libraries when tested to space quality grades • Up to 1.6M Used Gates and 596 Pads with 3.3 V, 3V and 2.5V libraries when tested to	Original		PDF
LAH3 Abstract: No abstract text available Text: P jjp i G E C P L E S S E Y SE MI C ON DU CT ORS DS3596-2.4 MA9000A Sea of Gates RADIATION HARD ADVANCED GATE ARRAY DESIGN SYSTEM The logic building block is a cell-unit, equivalent ¡n size to a two input NAND gate. Back-to-back cell units form the core of	OCR Scan	DS3596-2 MA9000A 37bfl522 MA9000A 002H24T LAH3	PDF
3-input xnor Abstract: 32 data input multiplexer explanation 1 bit full adder "asynchronous Dual-Port RAM" 1-INPUT NAND SCHMITT TRIGGER AT40K AT40KAL AT94K 3-input-XOR 4-input OR gates ttl Text: PSLI Macro Library Features • Functional Macros • Dynamic Macros Description The Programmable System Level Integrated PSLI library of components can be divided into 2 types of macros: functional and dynamic. Functional macros are components with fixed functionality, such as the 2-input AND gate. Dynamic macros are	Original	12/01/xM 3-input xnor 32 data input multiplexer explanation 1 bit full adder "asynchronous Dual-Port RAM" 1-INPUT NAND SCHMITT TRIGGER AT40K AT40KAL AT94K 3-input-XOR 4-input OR gates ttl	PDF
AOI222 Abstract: AOI2223 AOI222H MH1099 MH1242 0.35-um CMOS standard cell library inverter Text: Features • High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 Nominal • Up to 1.6 Million Used Gates and 596 Pads, with 3.3V, 3V, and 2.5V Libraries • System Level Integration Technology Cores on Request: SRAM and TRAM (Gate Level or Embedded) • I/O Interfaces:	Original	5962-01B01 4138E AOI222 AOI2223 AOI222H MH1099 MH1242 0.35-um CMOS standard cell library inverter	PDF
T157WG Abstract: S-MOS navnet A138G2 t177 4-bit full adder using nand gates and 3*8 decoder 6 input or gate SLA1024 T161RE Text: S-M 0 S S Y S T E M S INC 5bE J> m 7 ci3 Z eÏQ'l GG01522 fc.35 H S I 1 0 SLA1 OOOO Series HIGH SPEED CMOS GATE ARRAYS • DESCRIPTION The S-MOS SLA10000 series is a channel-less gate array manufactured on S-MOS’ state-of-the-art 0.8 micron double-metal SiCMOS process. The series consists of 11 arrays ranging from 9,000 to 101,800 usable gates and	OCR Scan	GG01522 SLA10000 SSC5000 B8259 B8237 B82284 B8255 T157WG S-MOS navnet A138G2 t177 4-bit full adder using nand gates and 3*8 decoder 6 input or gate SLA1024 T161RE	PDF
O2-A2 Abstract: CLA60000 16-LINE TO 4-LINE PRIORITY ENCODERS DRF4T101 4 bit binary multiplier Gray to BCD converter CLA5000 J K flip-flop CLA64 design octal counter using j-k flipflop Text: CLA60000 Series Channel less CMOS Gate Arrays This new family of gate arrays uses many innovative techniques to achieve 110K gates per chip with system clock speeds of up to 70MHz. The combination of high speed, high gate complexity and low power operation places Zarlink Semiconductor	Original	CLA60000 70MHz. O2-A2 16-LINE TO 4-LINE PRIORITY ENCODERS DRF4T101 4 bit binary multiplier Gray to BCD converter CLA5000 J K flip-flop CLA64 design octal counter using j-k flipflop	PDF
CLA60000 Abstract: zarlink cla5000 CLA5000 16-LINE TO 4-LINE PRIORITY ENCODERS 4 bit binary multiplier CLA5000 Series Zarlink gate array RAD32D MVA50 Text: CLA60000 Series Channel less CMOS Gate Arrays This new family of gate arrays uses many innovative techniques to achieve 110K gates per chip with system clock speeds of up to 70MHz. The combination of high speed, high gate complexity and low power operation places Zarlink Semiconductor	Original	CLA60000 70MHz. zarlink cla5000 CLA5000 16-LINE TO 4-LINE PRIORITY ENCODERS 4 bit binary multiplier CLA5000 Series Zarlink gate array RAD32D MVA50	PDF

TRISTATE NAND GATE Search Results

TRISTATE NAND GATE Result Highlights (5)

TRISTATE NAND GATE Datasheets Context Search

tristate xnor gate

octal Bilateral Switches

TTL 1-of-8 encoder

z63n

atmel 216

PO61

TEMIC PLD

transistor nd8

atmel 424

CB12000

circuit diagram of Tri-State Buffer using CMOS

Untitled

74AC367

Untitled

PO88

full adder circuit using nor gates

m6845

Transistor Equivalent list po55

LAH3

3-input xnor

AOI222

T157WG

O2-A2

CLA60000