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Abstract: GR-253-CORE GR-499-CORE XRT73L00 XRT73L00IV
Text: áç XRT73L00 E3/DS3/STS-1 LINE INTERFACE UNIT JULY 2001 REV. 1.2.0 FEATURES • Meets E3/DS3/STS-1 Jitter Tolerance Requirements GENERAL DESCRIPTION The XRT73L00 DS3/E3/STS-1 Line Interface Unit is designed to be used in DS3, E3 or SONET STS-1 applications and consists of a line transmitter and receiver integrated on a single chip.
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Abstract: No abstract text available
Text: áç XRT73L00 PRELIMINARY E3/DS3/STS-1 LINE INTERFACE UNIT SEPTEMBER 2000 REV. P1.0.3 FEATURES • Meets E3/DS3/STS-1 Jitter Tolerance Requirements GENERAL DESCRIPTION The XRT73L00 DS3/E3/STS-1 Line Interface Unit is designed to be used in DS3, E3 or SONET STS-1 applications and consists of a line transmitter and receiver integrated on a single chip.
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Abstract: GR-253-CORE GR-499-CORE XRT73L00 XRT73L00IV 110ORDERING
Text: áç XRT73L00 E3/DS3/STS-1 LINE INTERFACE UNIT APRIL 2001 REV. 1.1.0 FEATURES • Meets E3/DS3/STS-1 Jitter Tolerance Requirements GENERAL DESCRIPTION The XRT73L00 DS3/E3/STS-1 Line Interface Unit is designed to be used in DS3, E3 or SONET STS-1 applications and consists of a line transmitter and receiver integrated on a single chip.
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225feet
Abstract: No abstract text available
Text: XRT73L00 PRELIMINARY E3/DS3/STS-1 LINE INTERFACE UNIT NOVEMBER 2000 REV. P1.0.5 GENERAL DESCRIPTION FEATURES • Meets E3/DS3/STS-1 Jitter Tolerance Requirements The XRT73L00 DS3/E3/STS-1 Line Interface Unit is designed to be used in DS3, E3 or SONET STS-1 applications and consists of a line transmitter and receiver integrated on a single chip.
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Abstract: GR-253-CORE GR-499-CORE XRT73L00 XRT73L00IV
Text: áç XRT73L00 PRELIMINARY E3/DS3/STS-1 LINE INTERFACE UNIT AUGUST 2000 REV. P1.0.2 GENERAL DESCRIPTION The XRT73L00 DS3/E3/STS-1 Line Interface Unit is designed to be used in DS3, E3 or SONET STS-1 applications and consists of a line transmitter and receiver integrated on a single chip.
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