k1117
Abstract: R36W power transistor k1821 L46R k1518 k1117 transistor k2225 transistor k2225 k1317 transistor k1317
Text: AND8009/D ECLinPS Plus SPICE Modeling Kit Prepared by: Senad Lomigora, Paul Shockman ON Semiconductor Broadband Applications Engineering http://onsemi.com APPLICATION NOTE Schematic Information The kit contains representative input and output schematics, netlists, and waveform used for the ECLinPS
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AND8009/D
k1117
R36W
power transistor k1821
L46R
k1518
k1117 transistor
k2225 transistor
k2225
k1317
transistor k1317
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R36W
Abstract: k1420 N52C N38C l46r k0114 N53C transistor k1117 k2225 transistor transistors k2628
Text: AND8009/D ECLinPS Plus SPICE Modeling Kit Prepared by Senad Lomigora, Paul Shockman ON Semiconductor Broadband Applications Engineering http://onsemi.com APPLICATION NOTE Objective The objective of this kit is to provide customers with enough circuit schematic and SPICE parameter information
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AND8009/D
r14525
AND8009/D
R36W
k1420
N52C
N38C
l46r
k0114
N53C
transistor k1117
k2225 transistor
transistors k2628
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transistor r1010
Abstract: 555N pw-3n BF 245 A spice BF172 MJE 280 power transistor TT2120 BF192 transistor r1011 transistor D113
Text: AND8009/D ECLinPS Plus SPICE Modeling Kit Prepared by: Senad Lomigora, Paul Shockman ON Semiconductor Broadband Applications Engineering http://onsemi.com APPLICATION NOTE Objective Schematic Information The objective of ”AND8009 ECLinPS Plus SPICE Modeling Kit” is to provide sufficient circuit schematic and
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AND8009/D
AND8009
transistor r1010
555N
pw-3n
BF 245 A spice
BF172
MJE 280 power transistor
TT2120
BF192
transistor r1011
transistor D113
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k1213
Abstract: k1118 transistor k1317 k1117 K2225 k2225 transistor k0305 K0319 c1213 transistor k1117 transistor
Text: AND8009/D ECLinPS Plus SPICE Modeling Kit Prepared by Senad Lomigora, Paul Shockman ON Semiconductor Broadband Applications Engineering http://onsemi.com APPLICATION NOTE Objective The objective of this kit is to provide customers with enough circuit schematic and SPICE parameter information
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AND8009/D
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k1213
k1118
transistor k1317
k1117
K2225
k2225 transistor
k0305
K0319
c1213 transistor
k1117 transistor
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k2324
Abstract: k1821 k2225 k1317 power transistor k1821 k1213 k1117 k0313 k2225 transistor N13R
Text: AND8009/D ECLinPS Plus SPICE Modeling Kit Prepared by: Senad Lomigora, Paul Shockman ON Semiconductor Broadband Applications Engineering http://onsemi.com APPLICATION NOTE Schematic Information The kit contains representative input and output schematics, netlists, and waveform used for the ECLinPS
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AND8009/D
C0203
K0204
K0204WB
L01WB
L02WB
L03WB
k2324
k1821
k2225
k1317
power transistor k1821
k1213
k1117
k0313
k2225 transistor
N13R
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k1213
Abstract: K1118 k0312 k2225 transistor transistors k0317 transistors k2628 K1020 c1213 transistor transistor k1213 K1117
Text: AND8009/D ECLinPS Plus SPICE Modeling Kit Prepared by Senad Lomigora, Paul Shockman, Paul Hunt ON Semiconductor Logic Applications Engineering http://onsemi.com APPLICATION NOTE Objective The Objective of this kit is to provide customers with enough circuit schematic and SPICE parameter information
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AND8009/D
r14525
k1213
K1118
k0312
k2225 transistor
transistors k0317
transistors k2628
K1020
c1213 transistor
transistor k1213
K1117
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LQFP32
Abstract: LQFP-32 MC100 MC100EPT622 MC100EPT622FA MC100EPT622FAR2
Text: MC100EPT622 3.3V LVTTL/LVCMOS to LVPECL Translator The MC100EPT622 is a 10- Bit LVTTL/LVCMOS to LVPECL translator. Because LVPECL Positive ECL levels are used only +3.3 V and ground are required. The device has an OR- ed enable input which can accept either LVPECL (ENPECL) or TTL/LVCMOS inputs
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MC100EPT622
MC100EPT622
MC100
EPT622
LQFP-32
r14525
MC100EPT622/D
LQFP32
LQFP-32
MC100
MC100EPT622FA
MC100EPT622FAR2
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MC100EP90
Abstract: MC100EP90DT MC100EP90DTR2 MC10EP90 MC10EP90DT MC10EP90DTR2
Text: MC10EP90, MC100EP90 -3.3V / -5VĄTriple ECL Input to LVPECL/PECL Output Translator The MC10/100EP90 is a TRIPLE ECL TO LVPECL/PECL translator. The device receives differential LVECL or ECL signals and translates them to differential LVPECL or PECL output signals.
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MC10EP90,
MC100EP90
MC10/100EP90
r14525
MC10EP90/D
MC100EP90
MC100EP90DT
MC100EP90DTR2
MC10EP90
MC10EP90DT
MC10EP90DTR2
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N100
Abstract: NB100LVEP17 NB100LVEP17DT NB100LVEP17DTR2 NB100LVEP17MN TSSOP-20 qfn24 socket N100 transistor QFN-24
Text: NB100LVEP17 2.5V / 3.3V / 5V ECL Quad Differential Driver/Receiver The NB100LVEP17 is a 4-bit differential line receiver. The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications.
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NB100LVEP17
NB100LVEP17
r14525
NB100LVEP17/D
N100
NB100LVEP17DT
NB100LVEP17DTR2
NB100LVEP17MN
TSSOP-20
qfn24 socket
N100 transistor
QFN-24
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KEP05
Abstract: HEP05 MC100EP05 MC10EP05
Text: MC10EP05, MC100EP05 3.3V / 5VĄECL 2-Input Differential AND/NAND The MC10/100EP05 is a 2–input differential AND/NAND gate. The device is functionally equivalent to the EL05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP05 is ideal for applications requiring the fastest AC performance
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MC10EP05,
MC100EP05
MC10/100EP05
LVEL05
LVEL05
r14525
MC10EP05/D
KEP05
HEP05
MC100EP05
MC10EP05
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LVEP221
Abstract: NB100LVEP221 NB100LVEP221FA NB100LVEP221FAR2
Text: NB100LVEP221 2.5V/3.3V 1:20 Differential HSTL/ECL/PECL Clock Driver The NB100LVEP221 is a low skew 1-to-20 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The two clock inputs are differential
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NB100LVEP221
NB100LVEP221
1-to-20
LVEP221
r14525
NB100LVEP221/D
NB100LVEP221FA
NB100LVEP221FAR2
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HEP58
Abstract: MC100EP58 MC10EP58
Text: MC10EP58, MC100EP58 3.3V / 5VĄECL 2:1 Multiplexer The MC10/100EP58 is a 2:1 multiplexer. The device is pin and functionally equivalent to the EL58 and LVEL58 devices. The 100 Series contains temperature compensation. • 310 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical
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MC10EP58,
MC100EP58
MC10/100EP58
LVEL58
HEP58
KEP58
r14525
MC10EP58/D
HEP58
MC100EP58
MC10EP58
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MC100
Abstract: MC100E016 MC100EP016 MC100EP016A MC100EP016AFA MC100EP016AFAR2 25pe16
Text: MC100EP016A 3.3 VĄECL 8-Bit Synchronous Binary Up Counter The MC100EP016A is a high–speed synchronous, presettable, cascadeable 8–bit binary counter. Architecture and operation are the same as the ECLinPS family MC100E016 with higher operating speed.
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MC100EP016A
MC100EP016A
MC100E016
r14525
MC100EP016A/D
MC100
MC100EP016
MC100EP016AFA
MC100EP016AFAR2
25pe16
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EP809
Abstract: MC100EP809 MC100EP809FA MC100EP809FAR2 MC100 SY89809L
Text: MC100EP809 3.3VĄ1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable The MC100EP809 is a low skew 1–to–9 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The part is designed for use in low voltage
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MC100EP809
MC100EP809
r14525
MC100EP809/D
EP809
MC100EP809FA
MC100EP809FAR2
MC100
SY89809L
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D1875
Abstract: HVP16 KVP16 LVEL16 MC100LVEP16 MC10LVEP16
Text: MC10LVEP16, MC100LVEP16 2.5V / 3.3V ECL Differential Receiver/Driver The MC10/100LVEP16 is a world class differential receiver/driver. The device is functionally equivalent to the EL16, EP16 and LVEL16 devices. With output transition times significantly faster than the EL16
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MC10LVEP16,
MC100LVEP16
MC10/100LVEP16
LVEL16
LVEL16,
LVEP16
MC10LVEP16/D
D1875
HVP16
KVP16
LVEL16
MC100LVEP16
MC10LVEP16
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AND8020
Abstract: AND8040 MC100EP40 MC100EP40DT MC100EP40DTR2 j 3055
Text: MC100EP40 3.3V / 5VĄECL Differential Phase-Frequency Detector The MC100EP40 is a three–state phase–frequency detector intended for phase–locked loop applications which require a minimum amount of phase and frequency difference at lock. Advanced design
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MC100EP40
MC100EP40
r14525
MC100EP40/D
AND8020
AND8040
MC100EP40DT
MC100EP40DTR2
j 3055
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EP105
Abstract: MC100EP105 MC100EP105FA MC100EP105FAR2 MC10EP105 MC10EP105FA MC10EP105FAR2 marking CODE D2B
Text: MC10EP105, MC100EP105 3.3V / 5VĄECL Quad 2-Input Differential AND/NAND The MC10/100EP105 is a quad 2–input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device,
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MC10EP105,
MC100EP105
MC10/100EP105
LVEL05
LVEL05
EP105
EP105
r14525
MC10EP105/D
MC100EP105
MC100EP105FA
MC100EP105FAR2
MC10EP105
MC10EP105FA
MC10EP105FAR2
marking CODE D2B
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MC10EP01
Abstract: No abstract text available
Text: MC10EP016, MC100EP016 3.3V / 5VĄECL 8-Bit Synchronous Binary Up Counter The MC10/100EP016 is a high–speed synchronous, presettable, cascadeable 8–bit binary counter. Architecture and operation are the same as the MC10E016 in the ECLinPS family. The counter features internal feedback to TC gated by the TCLD
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MC10EP016,
MC100EP016
MC10/100EP016
MC10E016
r14525
MC10EP016/D
MC10EP01
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Untitled
Abstract: No abstract text available
Text: MC10EP451, MC100EP451 Product Preview 3.3V / 5VĄECL 6-Bit Differential Register with Master Reset The EP451 is a 6–bit fully differential register with common clock and single ended Master Reset MR . It is ideal for very high frequency applications where a registered data path is necessary.
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MC10EP451,
MC100EP451
EP451
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LQFP-64
Abstract: LVEP224 NB100LVEP224 NB100LVEP224FA NB100LVEP224FAR2
Text: NB100LVEP224 2.5V/3.3V 1:24 Differential ECL/PECL Clock Driver with Clock Select and Output Enable The NB100LVEP224 is a low skew 1-to-24 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The part is designed for use in low
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NB100LVEP224
NB100LVEP224
1-to-24
NB100LVEP224/D
LQFP-64
LVEP224
NB100LVEP224FA
NB100LVEP224FAR2
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EP11
Abstract: HEP11 KEP11 LVEL11 MC100EP11 MC10EP11
Text: MC10EP11, MC100EP11 3.3V / 5V ECL 1:2 Differential Fanout Buffer The MC10/100EP11 is a differential 1:2 fanout buffer. The device is pin and functionally equivalent to the LVEL11 device. With AC performance much faster than the LVEL11 device, the EP11 is ideal
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MC10EP11,
MC100EP11
MC10/100EP11
LVEL11
MC10EP11/D
EP11
HEP11
KEP11
MC100EP11
MC10EP11
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Untitled
Abstract: No abstract text available
Text: MC10EP196, MC100EP196 Product Preview 3.3V/5VĄECL Programmable Delay Chip with FTUNE The MC10/100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It is identical to the
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MC10EP196,
MC100EP196
MC10/100EP196
EP195
EP196
r14525
MC10E196/D
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PS2360
Abstract: No abstract text available
Text: MC100EP196 3.3VĄECL Programmable Delay Chip with FTUNE The MC100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides programmably variable delay of a differential ECL input signal. It has similar architecture to the EP195 with the added feature of further
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MC100EP196
EP195
EP196
r14525
MC100EP196/D
PS2360
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Untitled
Abstract: No abstract text available
Text: MC10EP17, MC100EP17 3.3V / 5VĄECL Quad Differential Driver/Receiver The MC10/100EP17 is a 4-bit differential line receiver based on the EP16 device. The >3.0 GHz maximum frequency provided by the high frequency outputs makes the device ideal for buffering of very high
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MC10EP17,
MC100EP17
MC10/100EP17
r14525
MC10EP17/D
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