SYNOPSYS DC ULTRA Search Results

SYNOPSYS DC ULTRA Result Highlights (5)

Part	Manufacturer	Description
LBUA5QJ2AB-828	Murata Manufacturing Co Ltd	QORVO UWB MODULE
LBUA5QJ2AB-828EVB	Murata Manufacturing Co Ltd	QORVO UWB MODULE EVALUATION KIT
LXMSJZNCMH-225	Murata Manufacturing Co Ltd	Ultra small RAIN RFID chip tag
LXMS21NCMH-230	Murata Manufacturing Co Ltd	Ultra small RAIN RFID chip tag
MGN1S1208MC-R7	Murata Manufacturing Co Ltd	DC-DC 1W SM 12-8V GAN

SYNOPSYS DC ULTRA Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
L9013Q13Q Abstract: MSM13Q floorplan io uart vhdl Text: MSM13Q0000/14Q0000 0.35 µm Sea of Gates Arrays DESCRIPTION Oki’s 0.3 5 µm ASIC products deliver ultra-high performance and high density at low power dissipation. The MSM13Q0000/14Q0000 series devices referred to as “MSM13Q/14Q” are implemented with the	Original	MSM13Q0000/14Q0000 MSM13Q0000/14Q0000 MSM13Q/14Q" MSM13Q) MSM14Q) 64-Mbit MSM13Q/14Q 1-800-OKI-6994 L9013Q13Q MSM13Q floorplan io uart vhdl	PDF
Untitled Abstract: No abstract text available Text: Oki Semiconductor MSM13Q/14Q 0.35 \|im Sea of Gates Arrays DESCRIPTION Oki's 0.3 5 Jim ASIC products deliver ultra-high performance and high density at low power dissipation. The M SM 13Q0000/14Q0000 series devices referred to as "M SM 13Q /14Q " are implemented with the	OCR Scan	MSM13Q/14Q 13Q0000/14Q0000 MSM13Q) MSM14Q) 64-Mbit 13Q/14Q 28x28 32x32	PDF
IC380 Abstract: cypress FLASH370 pasic380 data entry FLASH370 verilog code for adder galaxy note lof file format cypress FLASH370 programming Text: Designing UltraLogict With Exemplar and Synopsyst Introduction Galileot from Exemplar Logic and the Design Compiler from Synopsyst provide two pathways for programmer logic users to use Cypress's UltraĆ Logict devices with thirdĆparty design environĆ ments. They provide behavioral Hardware DescripĆ	Original	FLASH370 IC380 cypress FLASH370 pasic380 data entry verilog code for adder galaxy note lof file format cypress FLASH370 programming	PDF
programming manual EPLD Abstract: 8 BIT ALU design with vhdl code using structural xilinx epld 16 bit carry lookahead subtractor vhdl ABEL-HDL Reference Manual EPLD cb8cle programmer EPLD XC7000 XC7336 Text: Getting Started with Xilinx EPLDs Designing with EPLDs Compiling Your Design X2845 Fitting Your Design Xilinx Synopsys Interface EPLD User Guide Simulating Your Design EPLD Architecture Library Component Specifications Attributes Xilinx Synopsys Interface EPLD User Guide — December, 1994 0401289 01	Original	X2845 XC2064, XC3090, XC4005, XC-DS501 programming manual EPLD 8 BIT ALU design with vhdl code using structural xilinx epld 16 bit carry lookahead subtractor vhdl ABEL-HDL Reference Manual EPLD cb8cle programmer EPLD XC7000 XC7336	PDF
MSM13Q Abstract: msm 32X32 Text: Oki Semiconductor MSM13Q/14Q 0.35 \|im Sea of Gates Arrays D E SC R IP TIO N O ki's 0.3 5 \|_im ASIC products deliver ultra-high performance and high density at low power dissipation. The M SM 13Q 0000/14Q 0000 series devices referred to as "M SM 1 3 Q /1 4 Q " are im plem ented with the	OCR Scan	MSM13Q/14Q MSM13Q0000/14Q0000 MSM13Q/14Q" MSM13Q) MSM14Q) 64-Mbit MSM13Q/14Q 28x28 MSM13Q msm 32X32	PDF
verilog code for UART with BIST capability Abstract: VHDL CODE FOR HDLC controller ARM dual port SRAM compiler DesignWare SPI vhdl code for watchdog timer of ATM vhdl coding for analog to digital converter Sun Enterprise 250 static SRAM single-port verilog code for 16 bit risc processor verilog code arm processor Text: GS30 0.15-µm CMOS Standard Cell/Gate Array Version 0.2 May 16, 2000 Copyright  Texas Instruments Incorporated, 2000 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the	Original		PDF
NEC-V850 Abstract: DesignWare SPI vhdl code for watchdog timer of ATM ARM dual port SRAM compiler vhdl coding for analog to digital converter LogicVision verilog for SRAM 512k word 16bit uart verilog lvds synopsys on-chip modeling Text: GS30 0.15-µm CMOS Standard Cell/Gate Array Version 1.0 February, 2001 Copyright  Texas Instruments Incorporated, 2001 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the	Original	SRST145 NEC-V850 DesignWare SPI vhdl code for watchdog timer of ATM ARM dual port SRAM compiler vhdl coding for analog to digital converter LogicVision verilog for SRAM 512k word 16bit uart verilog lvds synopsys on-chip modeling	PDF
ahb arbiter in mentor Abstract: 16x16x1.4 Text: GS40 0.11-µm CMOS Standard Cell/Gate Array Version 0.5 May 19, 2000 Copyright  Texas Instruments Incorporated, 2000 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the	Original		PDF
144 QFP body size Abstract: 35x35 bga BGA and QFP Package vhdl code for usart DesignWare SPI 0.18-um CMOS technology characteristics ARM7 verilog code NEC-V850 PZT driver design vhdl coding for analog to digital converter Text: GS20 0.18-µm CMOS Standard Cell/Gate Array Version 1.0 April 6, 1999 Copyright  Texas Instruments Incorporated, 1999 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the	Original		PDF
ARM dual port SRAM compiler Abstract: designware i2c verilog code voltage regulator NEC-V850 ARM10 ARM946 TMS320C54X fastscan TI ASIC gs40 LogicVision Text: GS40 0.11-µm CMOS Standard Cell/Gate Array Version 1.0 January 29, 2001 Copyright  Texas Instruments Incorporated, 2001 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the	Original	SRST143 ARM dual port SRAM compiler designware i2c verilog code voltage regulator NEC-V850 ARM10 ARM946 TMS320C54X fastscan TI ASIC gs40 LogicVision	PDF
ARM dual port SRAM compiler Abstract: rm2510 synopsys dc ultra DSPG 16C450 16C550 ARM920T ARM940T IEEE1284 STD110 Text: V S MSUNG STD130 ELECTRONICS STD130 Standard Cell 0.18um System-On-Chip ASIC Dec 2000, V2.0 Features 1.8/2.5/3.3V - Leff= 0.15um, Ldrawn = 0.18um Device - Up to 23 million gates - Power dissipation :24nW/MHz 3.3/5.0V - Gate Delay : 48ps @ 1.8V, 1SL Device	Original	STD130 STD130 24nW/MHz ARM920T/ARM940T, ARM dual port SRAM compiler rm2510 synopsys dc ultra DSPG 16C450 16C550 ARM920T ARM940T IEEE1284 STD110	PDF
DSPG Abstract: Samsung Soc processor STD110 ASIC 16C450 16C550 ARM920T ARM940T IEEE1284 STD110 piler Text: V S MSUNG STD131 ELECTRONICS STD131 Standard Cell 0.18um System-On-Chip ASIC Dec 2000, V2.0 Features 1.8/2.5/3.3V - Leff= 0.15um, Ldrawn = 0.18um Device - Up to 23 million gates - Power dissipation :24nW/MHz 3.3/5.0V - Gate Delay : 48ps @ 1.8V, 1SL Device	Original	STD131 STD131 24nW/MHz ARM920T/ARM940T, DSPG Samsung Soc processor STD110 ASIC 16C450 16C550 ARM920T ARM940T IEEE1284 STD110 piler	PDF
synopsys Platform Architect Abstract: clock tree balancing DesignWare SPI vhdl code for watchdog timer of ATM 0.18-um CMOS technology characteristics vhdl coding for analog to digital converter CML Vterm 27x27 Text: GS20 0.18-µm CMOS Standard Cell/Gate Array Version 1.1 May 19, 2000 Copyright  Texas Instruments Incorporated, 2000 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the	Original		PDF
synopsys leda tool Abstract: hapstrak astro tools synopsys of counter project Text: Identify Actel Edition Quick Start Guide September 2009 http://solvnet.synopsys.com Disclaimer of Warranty Synopsys, Inc. makes no representations or warranties, either expressed or implied, by or with respect to anything in this manual, and shall not be liable	Original		PDF

datasheet of BGA Staggered pins Abstract: NEC-V850 VHDL CODE FOR HDLC controller vhdl code for 4 channel dma controller clock tree balancing serdes transceiver 1999 verilog code for i2c vhdl code download for memory in cam vhdl code for watchdog timer of ATM vhdl coding for analog to digital converter Text: GS30 0.15-µm CMOS Standard Cell/Gate Array High-Value ASIC ❑ 0.15-µm Leff process 0.18-µm drawn with Shallow Trench Isolation (STI) Inline bond pads Minimum height I/Os Minimum width I/O ❑ 4 and 5 levels of metal ❑ 6 million random logic gates plus 6 million	Original		PDF
ternary content addressable memory VHDL Abstract: ARM1020E SMART ASIC bga ARM dual port SRAM compiler Samsung ASIC 0.13um standard cell library Standard Cell 0.13um System-On-Chip ASIC DSPG samsung lcd JTAG "content addressable memory" precharge Text: V S MSUNG STDL150 ELECTRONICS STDL150 Standard Cell 0.13um System-On-Chip ASIC March 2003, V2.0 Features Analog cores - Ldrawn = 0.13um 1.5/2.5/3.3V Device 1.5/2.5/3.3V - Up to 45.8 million gates Interface - Power dissipation: 13nW/MHz@1.5V, 2SL, ND2 5.0V	Original	STDL150 STDL150 13nW/MHz ARM920T/ARM940T, ternary content addressable memory VHDL ARM1020E SMART ASIC bga ARM dual port SRAM compiler Samsung ASIC 0.13um standard cell library Standard Cell 0.13um System-On-Chip ASIC DSPG samsung lcd JTAG "content addressable memory" precharge	PDF
MSM13Q Abstract: L9013Q13Q Text: DATA SHEET O K I A S I C P R O D U C T S MSM13/14Q 0.35 µm Sea of Gates Arrays August 2002 • ■ –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––	Original	MSM13/14Q MSM13Q/14Q MSM13Q0000/14Q0000 MSM13Q/14Q" MSM13Q) MSM13Q L9013Q13Q	PDF
verilog code for 32 bit risc processor Abstract: vhdl code for usart 35x35 bga Sun Enterprise 250 Sun Ultra 30 DesignWare SPI 0.18 um CMOS free vhdl code download for usart NEC-V850 PZT driver design Text: GS30TR 0.15-µm CMOS Standard Cell/Gate Array Version 1.0 September 23, 1999 Copyright  Texas Instruments Incorporated, 1999 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the	Original	GS30TR verilog code for 32 bit risc processor vhdl code for usart 35x35 bga Sun Enterprise 250 Sun Ultra 30 DesignWare SPI 0.18 um CMOS free vhdl code download for usart NEC-V850 PZT driver design	PDF
ARM9TDMI Abstract: ARM1020E samsung hdd Samsung S ARM teaklite DSPG SMART ASIC bga ARM920t datasheet Avant Electronics USB samsung Text: V S MSUNG STDH150 ELECTRONICS STDH150 Standard Cell 0.13um System-On-Chip ASIC Dec 2001, V1.0 Features Analog cores - Ldrawn = 0.13um 1.2/2.5/3.3V Device - Up to 34.3 million gates - Power dissipation:9nW/[email protected], 2SL, ND2 3.3/5.0V - Gate Delay: 52ps @ 1.2V, 2SL, ND2	Original	STDH150 STDH150 ARM920T/ARM940T, ARM9TDMI ARM1020E samsung hdd Samsung S ARM teaklite DSPG SMART ASIC bga ARM920t datasheet Avant Electronics USB samsung	PDF
ARM dual port SRAM compiler Abstract: DSPG teaklite ARM9TDMI ARM1020E samsung hdd UART 16C450 Standard Cell 0.13um System-On-Chip ASIC ARM920T ARM926EJ Text: V S MSUNG STD150 ELECTRONICS STD150 Standard Cell 0.13um System-On-Chip ASIC Oct 2001, V1.0 Features Analog cores - Ldrawn = 0.13um 1.2/2.5/3.3V Device - Up to 46 million gates - Power dissipation:9nW/[email protected], 2SL, ND2 3.3/5.0V - Gate Delay: 52ps @ 1.2V, 2SL, ND2	Original	STD150 STD150 ARM920T/ARM940T, ARM dual port SRAM compiler DSPG teaklite ARM9TDMI ARM1020E samsung hdd UART 16C450 Standard Cell 0.13um System-On-Chip ASIC ARM920T ARM926EJ	PDF
ARM1020E Abstract: samsung hdd Samsung Soc processor 4468 8 pin ARM920t datasheet ARM9TDMI DSPG ARM SRAM compiler UART 16C450 ARM940T Text: V S MSUNG STD150 ELECTRONICS STD150 Standard Cell 0.13um System-On-Chip ASIC Oct 2001, V1.0 Features Analog cores - Ldrawn = 0.13um 1.2/2.5/3.3V Device - Up to 46 million gates - Power dissipation:9nW/[email protected], 2SL, ND2 3.3/5.0V - Gate Delay: 52ps @ 1.2V, 2SL, ND2	Original	STD150 STD150 ARM920T/ARM940T, ARM1020E samsung hdd Samsung Soc processor 4468 8 pin ARM920t datasheet ARM9TDMI DSPG ARM SRAM compiler UART 16C450 ARM940T	PDF
1117 transistor 0340 180 Abstract: M13Q floorplan io uart vhdl MSM13Q Text: MSM13/14Q 35µm DS 9…9/14Backup Page -1 Friday, November 21, 1997 11.17 a DATA SHEET O K I A S I C P R O D U C T S MSM13Q0000/14Q0000 0.35 µm Sea of Gates Arrays November 1997 MSM13/14Q 35µm DS 9…9/14Backup Page 0 Friday, November 21, 1997 11.17 a MSM13/14Q 35µm DS 9…9/14Backup Page 1 Friday, November 21, 1997 11.17 a	Original	MSM13/14Q 9/14Backup MSM13Q0000/14Q0000 MSM13Q/14Q MSM13Q0000/14Q0000 MSM13Q/14Q" 1117 transistor 0340 180 M13Q floorplan io uart vhdl MSM13Q	PDF
8x4 multiplexor Abstract: m3189 A500K VHDL vhdl code of ripple carry adder verilog code pipeline ripple carry adder verilog code for carry look ahead adder signal path designer Text: Synopsys Design Compiler for ProASIC Synthesis Guide Windows and UNIX Environments Actel Corporation, Sunnyvale, CA 94086 2000 by Actel Corporation. All rights reserved. Printed in the United States of America Part Number: 5579028-0 Release: September 2000	Original		PDF
MSM13Q Abstract: base cell floorplan io uart vhdl Text: DATA SHEET O K I A S I C P R O D U C T S MSM13Q/14Q000 0.35 µm Sea of Gates Arrays November 1999 • ■ –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––	Original	MSM13Q/14Q000 MSM13Q0000/14Q0000 MSM13Q0000/14Q0000 MSM13Q/14Q" MSM13enue 1-800-OKI-6388 MSM13Q base cell floorplan io uart vhdl	PDF

SYNOPSYS DC ULTRA Search Results

SYNOPSYS DC ULTRA Result Highlights (5)

SYNOPSYS DC ULTRA Datasheets Context Search

L9013Q13Q

Untitled

IC380

programming manual EPLD

MSM13Q

verilog code for UART with BIST capability

NEC-V850

ahb arbiter in mentor

144 QFP body size

ARM dual port SRAM compiler

ARM dual port SRAM compiler

DSPG

synopsys Platform Architect

synopsys leda tool

datasheet of BGA Staggered pins

ternary content addressable memory VHDL

MSM13Q

verilog code for 32 bit risc processor

ARM9TDMI

ARM dual port SRAM compiler

ARM1020E

1117 transistor 0340 180

8x4 multiplexor

MSM13Q